Subject: Re: [sv-ec] Re: $wait_all/any/... (Forward of bounced email from Arturo Salz)
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Thu Dec 19 2002 - 16:31:10 PST
> From: "Steven Sharp" <sharp@cadence.com>
>
>
> >The difference between $wait_all(x,y,z) and @(x && y && z) is that =
> >$wait_all actually works whereas the second form doesn't work. Most Verilog
> >compilers will = flag that expression as an error, and even if they don't,
> >it won't work because = the events will not trigger at the same time.
>
> They better not flag it as an error, since it is legal Verilog. However,
> it doesn't mean anything involving events on the three objects. It means
> to wait for a change in the value of the expression (x && y && z).
>
> Steven Sharp
> sharp@cadence.com
[I tried it out - VCS did complain if you do "(x && y && z)" with events.]
What seems to be missing is the complemtary operator to "or", i.e. we should
be able to do something like:
always @ (x and y and z) ...
- when the events are persistent. That would also allow more complex
expressions like:
always @ ((a and b) or (c and d)) ...
I'm sure nobody wants to add "and" as a keyword, but I think it's the
logicical extension.
Kev.
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