Subject: Re: [sv-ec] Re: $wait_all/any/... (Forward of bounced email from Arturo Salz)
From: Stuart Sutherland (stuart@sutherland-hdl.com)
Date: Thu Dec 19 2002 - 17:01:13 PST
Kevin,
"and" is already a keyword, the built-in "and" primitive. Using it in a
sensitivity list would be consistent with "or" which is used as both a
built-in primitive and in a sensitivity list. I agree that the current
Verilog does not allow operations on event data types, and thus @(x && y &&
z) -- but the whole point here is that we are extending Verilog. Using
either "and" or "&&" does the extension with out introducing new keywords
or tokens.
Stu
At 04:31 PM 12/19/2002, Kevin Cameron x3251 wrote:
> > From: "Steven Sharp" <sharp@cadence.com>
> >
> >
> > >The difference between $wait_all(x,y,z) and @(x && y && z) is that =
> > >$wait_all actually works whereas the second form doesn't work. Most
> Verilog
> > >compilers will = flag that expression as an error, and even if they don't,
> > >it won't work because = the events will not trigger at the same time.
> >
> > They better not flag it as an error, since it is legal Verilog. However,
> > it doesn't mean anything involving events on the three objects. It means
> > to wait for a change in the value of the expression (x && y && z).
> >
> > Steven Sharp
> > sharp@cadence.com
>
>[I tried it out - VCS did complain if you do "(x && y && z)" with events.]
>
>What seems to be missing is the complemtary operator to "or", i.e. we should
>be able to do something like:
>
> always @ (x and y and z) ...
>
>- when the events are persistent. That would also allow more complex
>expressions like:
>
> always @ ((a and b) or (c and d)) ...
>
>I'm sure nobody wants to add "and" as a keyword, but I think it's the
>logicical extension.
>
>Kev.
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