Subject: Re: [sv-ec] Re: $wait_all/any/... (Forward of bounced email from Arturo Salz)
From: Arturo Salz (Arturo.Salz@synopsys.com)
Date: Thu Dec 19 2002 - 17:00:38 PST
Steven,
That might be true if x, y, z form a Boolean expression, which is not true for events.
If you try to do that, you'll get these errors:
--------------------------------------------------------------------------------
Verilog-XL:
Error! Illegal reference to event (x) [Verilog-SRETE]
"aa.v", 10: x
Error! Illegal reference to event (y) [Verilog-SRETE]
"aa.v", 10: y
Error! Illegal reference to event (z) [Verilog-SRETE]
"aa.v", 10: z
--------------------------------------------------------------------------------
NC-Verilog:
@(x && y && z);
|
ncvlog: *E,EVNOTR (aa.v,10|6): an event is not a legal rvalue [9.7.3(IEEE)].
@(x && y && z);
|
ncvlog: *E,EVNOTR (aa.v,10|11): an event is not a legal rvalue [9.7.3(IEEE)].
@(x && y && z);
|
ncvlog: *E,EVNOTR (aa.v,10|16): an event is not a legal rvalue [9.7.3(IEEE)].
--------------------------------------------------------------------------------
MTI:
ERROR: aa.v(10): Illegal reference to event: x
ERROR: aa.v(10): Illegal reference to event: y
ERROR: aa.v(10): Illegal reference to event: z
--------------------------------------------------------------------------------
VCS:
Error: incorrect use of event x (aa.v line 10)
Error: incorrect use of event y (aa.v line 10)
Error: incorrect use of event z (aa.v line 10)
--------------------------------------------------------------------------------
Arturo
----- Original Message -----
From: "Steven Sharp" <sharp@cadence.com>
To: <sv-ec@eda.org>; <david.smith@synopsys.COM>
Sent: Thursday, December 19, 2002 3:32 PM
Subject: Re: [sv-ec] Re: $wait_all/any/... (Forward of bounced email from Arturo Salz)
>The difference between $wait_all(x,y,z) and @(x && y && z) is that =
>$wait_all actually works whereas the second form doesn't work. Most Verilog
>compilers will = flag that expression as an error, and even if they don't,
>it won't work because = the events will not trigger at the same time.
They better not flag it as an error, since it is legal Verilog. However,
it doesn't mean anything involving events on the three objects. It means
to wait for a change in the value of the expression (x && y && z).
Steven Sharp
sharp@cadence.com
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