Subject: Re: [sv-ec] Re: $wait_all/any/... (Forward of bounced email from Arturo Salz)
From: Steven Sharp (sharp@cadence.com)
Date: Thu Dec 19 2002 - 16:52:45 PST
>[I tried it out - VCS did complain if you do "(x && y && z)" with events.]
OK, I missed the context that x, y and z are named events. Yes, it is
illegal to apply logical operators to events; they don't have values.
For any objects where it is legal to have such an expression, the event
control would wait on the value of the expression.
>I'm sure nobody wants to add "and" as a keyword, but I think it's the
>logicical extension.
"and" is already a keyword; it is a gate primitive, like "or" is. So
whatever I might think about the extension, it doesn't require adding
a keyword. You could even extend it to include "not", as well as the
less useful ""nand", "nor", "xor" and "xnor", without adding keywords.
Note that Verilog-2001 allows the use of a comma instead of an event-or
operator, removing any appearance of actual logic. This makes sense partly
because there isn't any useful "event-and" semantic, without these weird
persistent event things.
Steven Sharp
sharp@cadence.com
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