[sv-bc] Re: [sv-ac] SV-AC feedback for the next PAR

Please consider the following as well:

1. Parameters support in checker - just like module. Yes we can use "const"
ports as work-around, but parameters are so intuitive to Verilog/SV folks
(module, interface, class - all of them have it). If really needed I can
throw in some PPT with pros-and-cons of const vs. parameter - I really wish
it is not needed - MHO.

2. Just to explicitly state that "$display" etc, should be allowed (I
believe your "procedural statements" cover it, but just wanted to highlight
the pain from user angle of not having it in 2009 version)

3. When you say "checker instantiation in class" - are we now extending full
SVA (concurrent) to classes? This has been a CONSTANT requirement from as
many customers as I have spoken to - especially those from E background. If
not, please add this one.

4. Run time variable as delays: a ##variable_delay b; Again E had this for
decade+, one of the very frequently asked for feature by users (in forums,
our trainings etc.)

5. Optional: PSL vunit like inheritance?
6. As part of temporal coverage, can we bring in "binning" as well? Say I
have a ## {1:5] b --> Can I add cover the "bins" with 1,5, others as bins?
We recently found an interesting bug on a customer, live design - the range
was specified for a targeted multiplier architecture in micro-arch spec. But
RTL folks forgot/skipped it by mistake. Our team had manually "binned" this
temporal range and caught this "hole"! Very interesting application indeed!

7. How to extend the scope of SVA sequences to be used as "temporal
constraints" for SV-constraint random generation?

Thanks
Srini
www.cvcblr.com

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