[sv-bc] RE: [sv-ac] SV-AC feedback for the next PAR

From: Bresticker, Shalom <shalom.bresticker@intel.com>
Date: Wed Feb 17 2010 - 21:51:14 PST

Hi,

1. Parameters support in checker - just like module. Yes we can use "const" ports as work-around, but parameters are so intuitive to Verilog/SV folks (module, interface, class - all of them have it). If really needed I can throw in some PPT with pros-and-cons of const vs. parameter - I really wish it is not needed - MHO.
[SB] I think this is Mantis 2111
2. Just to explicitly state that "$display" etc, should be allowed (I believe your "procedural statements" cover it, but just wanted to highlight the pain from user angle of not having it in 2009 version)
[SB] $display specifically is the subject of Mantis 2897
Shalom
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Received on Wed Feb 17 21:52:46 2010

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