[sv-bc] SystemVerilog 3.1A Errata And IEEE P1800 Activities

Dear SystemVerilog Members,
        In order for us to transfer the LRM with the Errata and also to
determine the cost for the IEEE SystemVerilog LRM development, we need
your immediate help. I know that many of you, are implementing
SystemVerilog tools, using tools, and developing methodologies for
design and verification. We have established a bug tracking system, to
enter and process, errata and clarifications. Since Accellera
SystemVerilog 3.1A is a solid standard with an excellent LRM, one
milestone for P1800 WG is targeted to deliver an IEEE SystemVerilog
Draft LRM by September 2004. Four EDA members (Cadence, Mentor, Synopsys
and Verisity) were present at the P1800 WG meeting and have agreed to
enter known errata by July 16 in the Accellera tracking system.
        This is an urgent request asking everyone to participate in
providing errata/clarification (based on the rules/guidelines the SV
Chairs published in earlier emails and discussed in the June SV
meeting). This will allow us to determine the effort (and cost) required
to develop the First IEEE SystemVerilog Draft by September. The P1800 WG
has requested Accellera to deliver an IEEE formatted LRM with a list of
Errata/clarification. The P1800 WG has also requested Accellera to fund
this activity rather than attaching an additional fee to each P1800
member.

Best Regards

Vassilios
Received on Fri Jul 2 03:37:02 2004