Re: [sv-bc] SystemVerilog 3.1A Errata And IEEE P1800 Activities

I have one.

I'm writing from home and I don't have access to the web.

I looked a couple of days ago at the 'static prefix' description of
always_comb. I'm sorry to say it's almost uncomprehensible. I know what
it's supposed to mean from the correspondence when it was being worked on.
At least I think I know what it is supposed to mean. But even knowing in
advance the interpretation, I was unable to make the correspondence between
the description and the interpretation.

Someone who does not already know what it is supposed to mean is going to
have real trouble with it.

In addition to fixing the description, a couple of examples would greatly
help.

Thanks,
Shalom

On Fri, 2 Jul 2004 Vassilios.Gerousis@Infineon.Com wrote:

> Dear SystemVerilog Members,
> In order for us to transfer the LRM with the Errata and also to
> determine the cost for the IEEE SystemVerilog LRM development, we need
> your immediate help. I know that many of you, are implementing
> SystemVerilog tools, using tools, and developing methodologies for
> design and verification. We have established a bug tracking system, to
> enter and process, errata and clarifications. Since Accellera
> SystemVerilog 3.1A is a solid standard with an excellent LRM, one
> milestone for P1800 WG is targeted to deliver an IEEE SystemVerilog
> Draft LRM by September 2004. Four EDA members (Cadence, Mentor, Synopsys
> and Verisity) were present at the P1800 WG meeting and have agreed to
> enter known errata by July 16 in the Accellera tracking system.
> This is an urgent request asking everyone to participate in
> providing errata/clarification (based on the rules/guidelines the SV
> Chairs published in earlier emails and discussed in the June SV
> meeting). This will allow us to determine the effort (and cost) required
> to develop the First IEEE SystemVerilog Draft by September. The P1800 WG
> has requested Accellera to deliver an IEEE formatted LRM with a list of
> Errata/clarification. The P1800 WG has also requested Accellera to fund
> this activity rather than attaching an additional fee to each P1800
> member.
>
> Best Regards
>
> Vassilios
>
>

-- 
Shalom Bresticker                         Shalom.Bresticker @freescale.com
Design & Reuse Methodology                            Tel: +972 9  9522268
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