[sv-bc] Pls Clarify: Expression Sizing and assignment operators.

I hope I am not raising something that has been discussed already.

Section 7.7, D4 says that SystemVerilog follows the same sizing
rules as Verilog.

Consider:

a = b * (c+=3);

My question is: Does the size of the 2nd operand in the += assign
expression (32 bits) effect the size of the full expression ??
(I hope not)

I wish the LRM would specifically say a yes or no and explain it
since this is unique to SystemVerilog.


-- 
Krishna
408-215-6152