Re: [sv-bc] Pls Clarify: Expression Sizing and assignment operators.

The semantics of assignment expressions are described
at the top of p.71 in the balloting draft.  Here's
how I interpret them --

    a = b * (c+=3);

is

    a = b * (c=c+3);

is

    a = b * f(c,c+3);

where, for T==$typeof(c),

    function automatic T f(output T LHS, input T RHS);
      LHS = RHS;
      return LHS;
    endfunction

The assignment to c is a context independent of the
assignment to a.

-- Brad

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org]On Behalf Of
Krishna Garlapati
Sent: Friday, March 25, 2005 3:31 PM
To: sv-bc@eda.org
Subject: [sv-bc] Pls Clarify: Expression Sizing and assignment
operators.



I hope I am not raising something that has been discussed already.

Section 7.7, D4 says that SystemVerilog follows the same sizing
rules as Verilog.

Consider:

a = b * (c+=3);

My question is: Does the size of the 2nd operand in the += assign
expression (32 bits) effect the size of the full expression ??
(I hope not)

I wish the LRM would specifically say a yes or no and explain it
since this is unique to SystemVerilog.


-- 
Krishna
408-215-6152