RE: [sv-bc] assignment to input

Maybe I missed something.
Would not "input a" have to default to wire to be compatible with 1364?

Shalom


> -----Original Message-----
> From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org]
On
> Behalf Of Rich, Dave
> Sent: Tuesday, August 29, 2006 9:26 PM
> To: sv-bc@server.eda-stds.org
> Subject: RE: [sv-bc] assignment to input
> 
> In SystemVerilog, we tried to overcome this loophole by defining an
> input port of a variable as a continuous assignment, and since
variables
> can only have one CA, an input port could not be coerced to an output
or
> inout.
> 
> However, a change late in the IEEE 1800-2005 LRM made inputs
implicitly
> default to a wire kind, so that 'input reg a' is now treated as 'input
> wire reg a'
> 
> I doubt that anyone has implanted this change and would really like to
> revert it back to the way it was in 3.1a for this very reason. Wires
> should only be used where multiple drivers are required.
> 
> Dave