RE: [sv-bc] assignment to input

I believe this part of the discussion comes from a misinterpretation,
which is a good reason to clarify it explicitly in the LRM.

The statement in 12.3.8, 
"A port that is declared as ... output ... but used as an ... input ...
or inout may be coerced to inout," does not talk about reading an output
inside the module driving the output, because such reading does not
change its attribute of being an output.

It refers to the port's value being driven from outside the module, as
though it were an input. The question is whether the value driven from
outside propagates back into the driving module, in which case it is
really an inout, and thus may not in Verilog be a variable, but rather
must be a net.

Example:

module top;

wire a = 1 ;

sub sub(a);

endmodule


module sub(a) ;

output a ;
assign a = 0 ;

endmodule


Is top.sub.a equal to 0 or to X ?


Shalom


> -----Original Message-----
> From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org]
On
> Behalf Of Gordon Vreugdenhil
> Sent: Tuesday, August 29, 2006 9:21 PM
> To: Michael (Mac) McNamara
> Cc: Don Mills; Feldman, Yulik; Brad Pierce; sv-bc@server.eda-stds.org
> Subject: Re: [sv-bc] assignment to input
> 
> 
> 
> Michael (Mac) McNamara wrote:
> [...]
> > I personally like the ability to read from outputs, and find other
> > languages that forbid this to be not helpful.  The one clear case
> where
> > reading from an output is quite useful is in a $display or $monitor
of
> > the signals in a module.
> 
> As a side note, my understanding is that VHDL 200x will permit
> one to read an output so we might not want to "regress" to
> old VHDL semantics.... :-)
> 
> Gord.
> --
> --------------------------------------------------------------------
> Gordon Vreugdenhil                                503-685-0808
> Model Technology (Mentor Graphics)                gordonv@model.com