Re: [sv-bc] assignment to input

I think the Project Authorization Request (PAR)

       http://standards.ieee.org/guides/companion/part1.html#PAR

is only considered an upper bound, not a commitment about the final
deliverable.

-- Brad 

-----Original Message-----
From: Bresticker, Shalom [mailto:shalom.bresticker@intel.com] 
Sent: Monday, September 04, 2006 7:26 AM
To: Brad Pierce; sv-bc@eda-stds.org
Subject: RE: [sv-bc] assignment to input

Actually, there will be an attempt to merge the 2 LRMs, but it is not
clear that the attempt will succeed.

If the attempt does not succeed, does that mean that the PAR is violated
and the proposed standard would be rejected by the IEEE?

Shalom

> -----Original Message-----
> From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org]
On
> Behalf Of Brad Pierce
> Sent: Tuesday, August 29, 2006 11:08 PM
> To: sv-bc@server.eda-stds.org
> Subject: Re: [sv-bc] assignment to input
> 
> >I realize that this discussion group is SV but don't we still need to

> >be consistant unless otherwise noted.
> 
> This forum is also for Verilog, not just for its SystemVerilog 
> extensions.  As part of the new PAR, the two LRMs will be combined
into
> a single LRM.
> 
> -- Brad