[sv-bc] FW: [sv-ac] Updated proposal for 1641 (severity system tasks)

fyi

 

________________________________

From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On
Behalf Of Kulshrestha, Manisha
Sent: Saturday, March 10, 2007 1:22 AM
To: sv-ac@server.eda-stds.org
Subject: [sv-ac] Updated proposal for 1641 (severity system tasks)

 

Hi,

 

I have updated a proposal based on the discussion in the meeting. This
proposal does not distinguish usage of these tasks in assertion vs.
regular sequential code. All the information is printed based on where
the severity task is called.

 

Please send your feedback.

 

As we discussed in the meeting how a user can print information about
assertion from these tasks if the task is not directly inside action
block. Here is an example about how a task can be called from an action
block and print the error messages. I did not find any standard way for
these tasks to print file name and line number of the assertion
statement (although there are tool specific ways to do that). Hopefully
in future it will be possible in System Verilog itself. Here is an
example:

 

module test;

 

reg clk;
reg a;
reg [127:0] name;

 

initial
begin
 clk = 0;
 a = 0;
end

 

always #10 clk = ~clk;

 

MYASSERT:assert property (@(posedge clk) a) else
begin
   $swrite(name, "%m");
   myTask(name);
end

 

task automatic myTask(ref reg [127:0] assertName);
begin
   $error($time, ": assert %s failed", assertName);
end
endtask

 

endmodule

Thanks.

Manisha


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