RE: [sv-bc] part selects on arbitrary expressions

I agree. The difference is important for type compatibility, especially
if the type of the selected object is an unpacked array. The LRM doesn't
make it clear whether the following assignment is legal:

bit a;
bit b [1:0];
assign a = b[0];

A similar issue is with part selects, selecting one element only:

assign a = b[0:0];

--Yulik.

-----Original Message-----
From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org] On
Behalf Of Bresticker, Shalom
Sent: Friday, March 09, 2007 4:37 PM
To: Greg Jaxon
Cc: sv-bc@server.eda.org
Subject: RE: [sv-bc] part selects on arbitrary expressions

This is a side-point, but I don't think the LRM defines whether a
bit-select is a scalar or a 1-bit vector. I don't think it has ever
mattered.

Shalom

> > "Making bit and part selects operators that can act on any vector
> value
> > would also allow some strange syntax. Since the result of a bit or
> part
> > select is a vector, there would be nothing to prevent taking another
> bit
> > or part select of that result. That would allow things like
> r[i][j][k],
> > which might look like a reference to a multidimensional array, but
> is
> > just a bit-select of a bit-select of a bit-select.
> 
> I submit that the disturbing thing here is the silent treatment of
> a scalar as a one element vector.

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