Re: [sv-bc] udp latch table

>From: "Bresticker, Shalom" <shalom.bresticker@intel.com>

>28.5 has this example of the UDP table for a latch:
...
>The table looks wrong to me. Aren't the clock values reversed?

I was doing hardware design back in the era when that text would
have been written.  At the time, transparent latch enables were
usually active-low (i.e. transparent when the enable was 0).  The
reason may have been so that they would latch the value on the
positive edge, much like a posedge triggered flop.  Or it may
have been because most level-sensitive control inputs at the time
seemed to be active-low, perhaps because the inputs of some early
TTL logic family floated high when unconnected. 

Steven Sharp
sharp@cadence.com


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