RE: [sv-bc] udp latch table

Yeah, Yulik Feldman suggested a similar explanation.

But today we're smarter and if a signal is treated as active low, we
indicate that in the name, like writing rst_n instead of rst for an
active-low reset.

Anyone object to reversing the clock values in the table?

It had me scratching my head when I tried to understand it.

Shalom
 

> -----Original Message-----
> From: Steven Sharp [mailto:sharp@cadence.com] 
> Sent: Tuesday, September 18, 2007 8:20 PM
> To: sv-bc@eda-stds.org; Bresticker, Shalom
> Subject: Re: [sv-bc] udp latch table
> 
> 
> >From: "Bresticker, Shalom" <shalom.bresticker@intel.com>
> 
> >28.5 has this example of the UDP table for a latch:
> ...
> >The table looks wrong to me. Aren't the clock values reversed?
> 
> I was doing hardware design back in the era when that text 
> would have been written.  At the time, transparent latch 
> enables were usually active-low (i.e. transparent when the 
> enable was 0).  The reason may have been so that they would 
> latch the value on the positive edge, much like a posedge 
> triggered flop.  Or it may have been because most 
> level-sensitive control inputs at the time seemed to be 
> active-low, perhaps because the inputs of some early TTL 
> logic family floated high when unconnected. 
> 
> Steven Sharp
> sharp@cadence.com
> 
---------------------------------------------------------------------
Intel Israel (74) Limited

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.