[sv-bc] Unconnected ports using .name implicit ports (SVDB 1660??)

Hi, All -

Shalom pointed out SVDB 1660. I'm not sure if it is clear that 
unconnected ports must be explicitly listed as empty ports (i.e. 
...  .port1(), ... when instantiating a module with an unconnected 
port. What do SV-BC members think?

Regards - Cliff

At 07:30 AM 10/15/2007, Bresticker, Shalom wrote:
>Cliff,
>
> > Clarify the .name implicit ports require unconnected ports to be
> > listed in the instantiation.
>
>Was this resolved by Mantis 1660?
>
>Regards,
>Shalom

----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, SystemVerilog, Synthesis and Verification Training


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