[sv-bc] RE: [sv-ec] Upward referencing rules question

(This is an sv-bc issue)

No, searching has always been upwards in the hierarchy; hence the name
of the section describing this feature has always been called "upwards
name referencing"

The module a1 in the example is not on an upwards path to the root of
the hierarchy from the reference.

Dave


> -----Original Message-----
> From: Steven Sharp [mailto:sharp@cadence.com]
> Sent: Monday, February 11, 2008 4:22 PM
> To: Rich, Dave; shalom.bresticker@intel.com; sv-ec@eda.org;
> danielm@aldec.com.pl
> Subject: RE: [sv-ec] Upward referencing rules question
> 
> 
> >From: "danielm" <danielm@aldec.com.pl>
> 
> >So if this reference found as first wouldn't be a variable - then
search
> >should proceed? below example shold work and print '5' ? :
> 
> Yes.  It must work this way, because this is how Verilog has always
> worked for this case.
> 
> 
> Steven Sharp
> sharp@cadence.com


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