RE: [sv-bc] Upward referencing rules question

Actually, implementations differ on this case. Some print 5, some give
an error.

Shalom
 

> No, searching has always been upwards in the hierarchy; hence 
> the name of the section describing this feature has always 
> been called "upwards name referencing"
> 
> The module a1 in the example is not on an upwards path to the 
> root of the hierarchy from the reference.
> 
> Dave
> 
> 
> > -----Original Message-----
> > From: Steven Sharp [mailto:sharp@cadence.com]
> > Sent: Monday, February 11, 2008 4:22 PM
> > To: Rich, Dave; shalom.bresticker@intel.com; sv-ec@eda.org; 
> > danielm@aldec.com.pl
> > Subject: RE: [sv-ec] Upward referencing rules question
> > > > 
> > >From: "danielm" <danielm@aldec.com.pl>
> > 
> > >So if this reference found as first wouldn't be a variable - then
> search
> > >should proceed? below example shold work and print '5' ? :
> > 
> > Yes.  It must work this way, because this is how Verilog has always 
> > worked for this case.
---------------------------------------------------------------------
Intel Israel (74) Limited

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.


-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.