[sv-bc] RE: [sv-ec] Upward referencing rules question

So lets change the example no a1 is on upward path? Now a1.foo() should be
found or not:

module M;
endmodule
 

module sub1;
    function int foo(input int i);
        return i; 
    endfunction
endmodule


module sub2;
 M a1();
 initial begin : oo
 $display(a1.foo(5));        
 end
endmodule 

module top;
	sub1 a1();
	sub2 uut();
endmodule

DANiel

-----Original Message-----
From: Rich, Dave [mailto:Dave_Rich@mentor.com] 
Sent: Tuesday, February 12, 2008 7:51 AM
To: Steven Sharp; shalom.bresticker@intel.com; danielm@aldec.com.pl
Cc: sv-bc@eda.org
Subject: RE: [sv-ec] Upward referencing rules question

(This is an sv-bc issue)

No, searching has always been upwards in the hierarchy; hence the name of
the section describing this feature has always been called "upwards name
referencing"

The module a1 in the example is not on an upwards path to the root of the
hierarchy from the reference.

Dave


> -----Original Message-----
> From: Steven Sharp [mailto:sharp@cadence.com]
> Sent: Monday, February 11, 2008 4:22 PM
> To: Rich, Dave; shalom.bresticker@intel.com; sv-ec@eda.org; 
> danielm@aldec.com.pl
> Subject: RE: [sv-ec] Upward referencing rules question
> 
> 
> >From: "danielm" <danielm@aldec.com.pl>
> 
> >So if this reference found as first wouldn't be a variable - then
search
> >should proceed? below example shold work and print '5' ? :
> 
> Yes.  It must work this way, because this is how Verilog has always 
> worked for this case.
> 
> 
> Steven Sharp
> sharp@cadence.com


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