Hi, 1. Consider the scenario, module test(output reg [7:0] out1); reg [3:0]in1,in2; typedef reg[7:0] myreg; always @(*) begin in2 = 4'b0101 ; in1 = 4'b1100 ; out1 = byte'(in2 -in1); end endmodule According to my understanding the value of out1 will be 00001001 . 2. Consider another scenario, module test(output reg [7:0] out1); reg signed [3:0]in1,in2; typedef reg[7:0] myreg; always @(*) begin in2 = 4'b0101 ; in1 = 4'b1100 ; out1 = byte'(in2 -in1); end endmodule According to my understanding the value of out1 will be 11111001 . 3. Consider another scenario, module test(output reg [7:0] out1); reg signed [3:0]in1,in2; typedef reg[7:0] myreg; always @(*) begin in2 = 4'b0101 ; in1 = 4'b1100 ; out1 = myreg'(in2 -in1); end endmodule According to my understanding the value of out1 will be 11111001 . 4. Consider another scenario, module test(output reg [7:0] out1); reg [3:0]in1,in2; typedef reg[7:0] myreg; always @(*) begin in2 = 4'b0101 ; in1 = 4'b1100 ; out1 = myreg'(in2 -in1); end endmodule According to my understanding the value of out1 will be 00001001 . Stanadard simulator behaviour is conflictiing and confusing for the above cases. Can anyone help me to find out the correct result for the above scenarios. Your response is important for me. Thanks & Regards, Sumay -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Mon May 12 09:32:47 2008
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