[sv-bc] RE: [sv-ec] query on evaluation of typecast expression

Sumay,

I think the LRM is already clear for examples like yours, in which the
casting type is explicit.

In such cases, the expression to be cast is evaluated in the context of
an assignment to a temp variable of the casting type.  The following

    out1 = byte'(in2 - in1);

is the same as declaring a temp 

    byte temp;

and doing

    temp = in2 - in1;
    out1 = temp;

I understand that some simulators are not in compliance with the LRM on
this point, but the LRM is clear.

4.14 says "A data type can be changed by using a cast ( ' ) operation.
In a static cast, the expression to be cast shall be enclosed in
parentheses that are prefixed with the casting type and an apostrophe.
If the expression is assignment compatible with the casting type, then
the cast shall return the value that a variable of the casting type
would hold after being assigned the expression."

-- Brad

-----Original Message-----
From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of
Sumay Guin
Sent: Monday, May 12, 2008 9:27 AM
To: sv-bc@eda.org; sv-ec@eda.org
Subject: [sv-ec] query on evaluation of typecast expression

Hi,


  1.  Consider the scenario,
       module test(output reg [7:0] out1);
       reg [3:0]in1,in2;
       typedef reg[7:0] myreg;
       always @(*)
       begin
       in2 = 4'b0101 ;
       in1 = 4'b1100 ;
       out1 = byte'(in2 -in1);
       end
      endmodule
      According to my understanding the  value of out1 will be  00001001
.

   2.  Consider another scenario,
       module test(output reg [7:0] out1);
       reg signed [3:0]in1,in2;
       typedef reg[7:0] myreg;
       always @(*)
       begin
       in2 = 4'b0101 ;
       in1 = 4'b1100 ;
       out1 = byte'(in2 -in1);
       end
      endmodule
      According to my understanding the  value of out1 will be  11111001

.     
 
  3. Consider another scenario,
       module test(output reg [7:0] out1);
       reg signed [3:0]in1,in2;
       typedef reg[7:0] myreg;
       always @(*)
       begin
       in2 = 4'b0101 ;
       in1 = 4'b1100 ;
       out1 = myreg'(in2 -in1);
       end
      endmodule
      According to my understanding the  value of out1 will be  11111001

.          
 
4.  Consider another scenario,
       module test(output reg [7:0] out1);
       reg [3:0]in1,in2;
       typedef reg[7:0] myreg;
       always @(*)
       begin
       in2 = 4'b0101 ;
       in1 = 4'b1100 ;
       out1 = myreg'(in2 -in1);
       end
       endmodule
       According to my understanding the  value of out1 will be
00001001 .

     Stanadard simulator behaviour is conflictiing and confusing for the

above cases.
     Can anyone help me to find out the correct result for the above 
scenarios.
     Your response is important for me.

Thanks & Regards,
Sumay



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