Re: [sv-bc] query on evaluation of typecast expression

>From: Sumay Guin <sumay@cal.interrasystems.com>

>  1.  Consider the scenario,
>       module test(output reg [7:0] out1);
>       reg [3:0]in1,in2;
>       typedef reg[7:0] myreg;
>       always @(*)
>       begin
>       in2 = 4'b0101 ;
>       in1 = 4'b1100 ;
>       out1 = byte'(in2 -in1);
>       end
>      endmodule
>      According to my understanding the  value of out1 will be  00001001 .

As Brad noted, a cast is equivalent to an assignment to a temporary
variable of the same type.  The target of an assignment is part of the
context of the expression being assigned, so the expression width will
be made to be 8 bits wide.  The operands of the subtract are context-
determined, so they will be converted to 8 bits before the subtract.
Both are unsigned, so the expression is unsigned.  Therefore the
conversions will be an unsigned conversions, or zero-extension.  The
value of 00000101-00001100 is 11111001.


>   2.  Consider another scenario,
>       module test(output reg [7:0] out1);
>       reg signed [3:0]in1,in2;
>       typedef reg[7:0] myreg;
>       always @(*)
>       begin
>       in2 = 4'b0101 ;
>       in1 = 4'b1100 ;
>       out1 = byte'(in2 -in1);
>       end
>      endmodule
>      According to my understanding the  value of out1 will be  11111001 
>.     

Here, the two operands are signed, so the expression is signed.  The
signedness of the target of the assignment does not affect the signedness
of the expression.  Therefore the conversions will be signed conversions,
or sign-extension.  The value of 00000101-11111100 is 00001001.
 
>  3. Consider another scenario,
>       module test(output reg [7:0] out1);
>       reg signed [3:0]in1,in2;
>       typedef reg[7:0] myreg;
>       always @(*)
>       begin
>       in2 = 4'b0101 ;
>       in1 = 4'b1100 ;
>       out1 = myreg'(in2 -in1);
>       end
>      endmodule
>      According to my understanding the  value of out1 will be  11111001 
>.          

The situation and result should be the same as scenario 2.  The only
significant difference between myreg and byte is that myreg is 4-state
and byte is 2-state, which doesn't matter here since the values are in
the 2-state value set.


>4.  Consider another scenario,
>       module test(output reg [7:0] out1);
>       reg [3:0]in1,in2;
>       typedef reg[7:0] myreg;
>       always @(*)
>       begin
>       in2 = 4'b0101 ;
>       in1 = 4'b1100 ;
>       out1 = myreg'(in2 -in1);
>       end
>       endmodule
>       According to my understanding the  value of out1 will be  00001001 .

The situation here is the same as scenario 1, and so is the result.  As
in scenario 1, the operands of the subtract are unsigned.


>     Stanadard simulator behaviour is conflictiing and confusing for the 
>above cases.
>     Can anyone help me to find out the correct result for the above 
>scenarios.
>     Your response is important for me.

I suspect that the results you are seeing are the correct results, since
the values you are expecting are incorrect.  If my explanations of the
reasons for the correct results are still confusing, you will have to
explain why you expected different results.

Steven Sharp
sharp@cadence.com


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