RE: [sv-bc] Verilog Std Ambiguity

This is section 10.3.3 in 1800-2009.

Shalom
 

> There seems to be an ambiguity in the Std for verilog.
> I don't have a copy of the System Verilog document, so I'll
> give a reference to 1364-2005:
> 
> The problem is in Section 6.1.3, concerning delays on assignments
> to vectors which permit multiple delays (therefore, to vector nets).
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