RE: [sv-bc] Verilog Std Ambiguity

From: Bresticker, Shalom <shalom.bresticker_at_.....>
Date: Tue Oct 13 2009 - 03:24:07 PDT
Hi,

This has a misquote. 

For the second item, transition to z, the delay used is the turn-off delay, not the rising delay.

Shalom


> To specify the delay to be used, 6.1.3 gives a three-part rule:
> 
>    If the RHS makes a transition to 0, the falling delay 
> shall be used.
>    If the RHS makes a transition to z, the rising delay shall be used.
>    In all other cases, the rising delay shall be used.
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Received on Tue Oct 13 03:30:12 2009

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