Re: [sv-bc] Verilog Std Ambiguity

Hi Shalom.

Right!  My mistake:  The turn-off delay is correct for the
second part.

Also, I now have reread the Std (1364.6.1.3) on this:

The question of whether individual bits should be
individually delayed when a vector net is assigned
also is poorly specified if not ambiguous.

The Std seems to imply that individual bits should
be delayed individually.   Perhaps the WG could not
agree on a direct statement?

Anyway, in the middle paragraph beginning with, "This
syntax, called a net delay, ...", the final sentence is:

   "Furthermore, if the assignment is to a vector net,
    then the rising and falling delays shall not be applied
    to the individual bits IF THE ASSIGNMENT IS INCLUDED
    IN THE DECLARATION". (upper-case emphasis is mine)

I would infer from this that in a continuous assignment to
a vector net not declared with delays, different delays
should be associated with different transitions of
individual bits.

Or, perhaps the intent is to leave it up to the simulator
developer, whether individual bits should be delayed
differently?  If so, I think this should be explicitly
stated.

I haven't used Verilog-XL for years, so I can't comment on
insight derived from it.   However, I think that a Std
should be driving tool development, and not vice-versa.
But, there's no reason for a Std to make tool development
unnecessarily difficult, either.

Bresticker, Shalom wrote:
> Hi,
> 
> This has a misquote. 
> 
> For the second item, transition to z, the delay used is the turn-off delay, not the rising delay.
> 
> Shalom
> 
> 
>> To specify the delay to be used, 6.1.3 gives a three-part rule:
>>
>>    If the RHS makes a transition to 0, the falling delay 
>> shall be used.
>>    If the RHS makes a transition to z, the rising delay shall be used.
>>    In all other cases, the rising delay shall be used.
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-- 
         John Michael Williams
         jwill@BasicISP.net


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