RE: [sv-bc] Verilog Std Ambiguity

Questa seems to behave like Verilog-XL and NC.

Shalom


> I should mention that Synopsys VCS and Aldec Active-HDL both 
> simulate as
> though interpretation II was the right one (it also is easier to
> implement the code according to II than to I).   My Mentor license has
> not yet been renewed, but I would assume that QuestaSim 
> (ModelSim) also
> would be implemented the same way.
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