[sv-bc] Verilog Std Ambiguity

Hi All.

There seems to be an ambiguity in the Std for verilog.
I don't have a copy of the System Verilog document, so I'll
give a reference to 1364-2005:

The problem is in Section 6.1.3, concerning delays on assignments
to vectors which permit multiple delays (therefore, to vector nets).

For example,
wire[31:0] C, A, B;
...
assign #(1,2,3) C = A & B; // or, assign #(4,5) C = A & B;

The 1364 Std assumes that any such assignment must be by a single
delay value, simultaneous to all bits -- as opposed to individual,
delayed transitions on each of the target vector's bits.

To specify the delay to be used, 6.1.3 gives a three-part rule:

   If the RHS makes a transition to 0, the falling delay shall be used.
   If the RHS makes a transition to z, the rising delay shall be used.
   In all other cases, the rising delay shall be used.

The ambiguity is in "makes":  Does this mean that the numerical
value of the whole RHS vector makes a transition to 0, or that
the RHS transition INCLUDES at least one bit going to 1'b0?
Similarly for 'z'?

I. Because the second rule refers to 'z' and is not folded into the
third rule, one would assume that the intent was to mean,
   If the RHS includes a transition of any bit to 0, the falling delay
shall be used.
   If the RHS includes a transition of any bit to z, the rising delay
shall be used, regardless of transitions to '0'.
   In all other cases, the rising delay shall be used.


II. However, it also is possible to interpret the rule to mean,
   If every bit in the RHS makes a transition to 0, the falling delay
shall be used.
   In all other cases, the rising delay shall be used.


If interpretation I is intended, I would suggest changing the rule to say,
   If the RHS includes a transition of any bit to 0, the falling delay
shall be used.
   In all other cases, the rising delay shall be used.

If interpretation II is intended, I would suggest rephrasing this rule
as it appears in II above.

It seems obvious that by default a transition of any bit to 'x'
should use the shortest delay, and a transition from a vector with any
bit 'x' to one with no bit 'x', should use the longest delay.   However,
perhaps an explicit cross-reference to 'x' transition rules should be
included?

I should mention that Synopsys VCS and Aldec Active-HDL both simulate as
though interpretation II was the right one (it also is easier to
implement the code according to II than to I).   My Mentor license has
not yet been renewed, but I would assume that QuestaSim (ModelSim) also
would be implemented the same way.

-- 
      John Michael Williams
      Senior Adjunct Faculty
Silicon Valley Technical Institute


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