RE: [sv-bc] Verilog Std Ambiguity

I checked a suite of customer tests, and only found one case of a
vector continuous assignment with more than a single delay.  But
that was being done to give a different turn-off delay.  The rise
and fall delays were the same.

Having different rise and fall delays isn't very useful if the choice
of delay is based on the LSB or the reduction-OR of the bits.  So it
isn't surprising that it isn't used much.

Steven Sharp
sharp@cadence.com


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