Accellera/ESD Alliance Co-Host “Remote Work, Remote Chip Design: Building Chips During a Pandemic”
Wednesday, June 9, 2021 9:00am-10:00am PT
The work-from-home (WFH) dynamic has created upheaval in all walks of life. This is particularly acute in the semiconductor industry, which has experienced unique challenges as engineers attempt complex chip innovation from their home offices.
Chip design and verification engineers, accustomed to having a range of robust software and hardware resources readily available within their physical office environment, are faced with new limitations. Their complicated and well-choregraphed verification flows and project cycles may have taken a hit given VPN tool and system access, Zoom-based team collaboration, and necessary deep thinking interrupted with everyday home activities.
Nonetheless, verification hasn’t stopped through the pandemic and its obstacles, as verification experts will discuss during this WFH panel sponsored by Accellera and SEMI/ESD Alliance. The panel will outline a set of Best Practices for chip design and verification engineers as they continue working from home, as well as the challenges of eventually getting back to the office.
Moderator Tom Fitzpatrick from Siemens EDA will explore the range of challenges and triumphs with a panel of verification engineers from a varied range of semiconductor disciplines and company sizes. The discussion will include modifications to development practices, coping with innovations requiring intense team collaboration, the ability to evaluate and implement new methodologies, dealing with necessary visits to the office labs, and the impact on product schedules.
- Martin Barnasconi, Technical Director System Design & Verification Methodologies, NXP
- Lu Dai, Senior Director of Engineering, Qualcomm
- Dr. Ashish Darbari, CEO, Axiomise
- Mark Glasser, Member of the Technical Staff, Cerebras
- Patrick Lynch, Senior Engineering Manager, Xilinx
The virtual format will include time for audience questions.
This event is sponsored by