Accellera Day at DVCon U.S.

Accellera Systems Initiative invites you to a special day dedicated to technical standards at the 2019 Design and Verification Conference U.S. in San Jose, CA. Join us Monday, February 25 starting at 9:00am to find out the latest in technologies that you can apply immediately and those that will help to define the future. Connect with experts and users as we learn, share, and network on the latest in standards innovations!

• Tutorial: "Gain Valuable Insight into the Changes and Features that are part of the new IEEE 1800.2 Standard for UVM and how to make the most of them"
• Accellera-sponsored Luncheon: Join us for an update on Accellera activities, presentation of the 2019 Technical Excellence award, and a SystemC-focused panel.
• Workshop: "SystemC: Focusing on High Level Synthesis and Functional Coverage for SystemC"
• DVCon Expo & Reception: Enjoy cocktails and conversations in a casual environment with the DVCon exhibitors.

Find out more >

UVM 2017-1.0 Now Available

New reference implementation is aligned with IEEE 1800.2

The Accellera Universal Verification Methodology (UVM) Working Group has released the UVM 2017-1.0 reference implementation. UVM 2017-1.0 is aligned with the IEEE 1800.2 standard and the enhancements that make it more powerful and easier to use. The working group has addressed some inconsistencies between the UVM Register Layer and other standards. It received a lot of feedback on the 0.9 release, and they were able to fix the bugs that were reported. UVM 2017-1.0 also includes full documentation of the API that is provided in addition to 1800.2-2017.

The UVM 2017-1.0 reference implementation can be downloaded for free from Accellera. The IEEE 1800.2-2017 standard is available free of charge from the IEEE Get program, courtesy of Accellera. Visit the UVM forum to provide feedback, ask questions, and engage in discussions. For more information on UVM, visit the UVM community page.

UVM Technical Tutorial

On April 11, 2017, the IEEE Standards Association (IEEE-SA) approved the IEEE 1800.2™ Standard for Universal Verification Methodology (UVM). For the tens of thousands of UVM verification engineers, this milestone connects teams to a standard recognized worldwide. The new IEEE-Compatible UVM Reference Implementation and Verification Components technical tutorial introduces you to the new reference implementation aligned with IEEE 1800.2 and created by the Accellera UVM Working Group. The speakers use the new reference implementation to describe the new features and changes relative to UVM 1.2. Viewers will learn the steps they need to take to update their verification components to be IEEE-compatible. Code examples will help viewers gain the practical knowledge they need to adopt the IEEE 1800.2™ Standard for UVM. View tutorial >