UVM-AMS Proposed Working Group

The Accellera Board of Directors recently approved the formation of a Proposed Working Group (PWG) to focus on the standardization of analog/mixed signal extensions (AMS) for the Universal Verification Methodology (UVM) standard. There have been various proposals presented at recent DVCon events addressing the need for AMS extensions for UVM to enrich and improve the verification of analog/mixed-signal products and applications. Most of these proposals offer similar capabilities, but often use different implementations to resolve existing constraints enforced by UVM or to address limitations caused by mixing languages such as SystemVerilog and Verilog-AMS. The objective of the PWG is to explore the need for standardized UVM mixed-signal extensions and offer a unified approach for mixed-signal verification.

For more information on the UVM-AMS PWG, visit here.

New Technical Tutorial Available: "Gain Valuable Insight into — and Make the Most Out of — the Changes and Features that Are Part of the New IEEE 1800.2 Standard for UVM"

Delivered at DVCon U.S. 2019 by Cliff Cummings of Sunburst Design, this tutorial dives into the changes and features that are part of the new IEEE 1800.2 standard for UVM. Cliff offers clarification and guidelines for UVM messaging and verbosities. He also explains the origins of the two different techniques to define UVM transactions and execute sequences, including the advantages and disadvantages of each. With this knowledge, viewers have a greater understanding of all publicly available UVM examples. Viewers also benefit from Cliff’s favorite UVM tips and tricks. View tutorial >