UVM-AMS Proposed Working Group

The Accellera Board of Directors recently approved the formation of a Proposed Working Group (PWG) to focus on the standardization of analog/mixed signal extensions (AMS) for the Universal Verification Methodology (UVM) standard. There have been various proposals presented at recent DVCon events addressing the need for AMS extensions for UVM to enrich and improve the verification of analog/mixed-signal products and applications. Most of these proposals offer similar capabilities, but often use different implementations to resolve existing constraints enforced by UVM or to address limitations caused by mixing languages such as SystemVerilog and Verilog-AMS. The objective of the PWG is to explore the need for standardized UVM mixed-signal extensions and offer a unified approach for mixed-signal verification.

The first UVM-AMS PWG meeting will be held Wednesday, May 22 at NXP Semiconductors, Schatzbogen 7, 81829 Munich, Germany. The meeting is planned from 10am to 4pm CEST and will cover presentations on industry best practices, discuss scope and requirements, and explore directions for standardization. Attendance is open to everyone, but registration is required. For more information on the UVM-AMS PWG, visit here.

SystemC Panel Discussion Available

At the annual Accellera Luncheon at DVCon U.S. 2019, Laurie Balch from Pedestal Research moderated a SystemC-focused panel that explored what’s next and what should be next for the SystemC standard. Panelists: Stuart Swan, Mentor, A Siemens Business; Filip Thoen, Synopsys, Inc.; Mike Meredith, Cadence Design Systems, Inc.; Mark Glasser, NVIDIA Corp.; and Martin Barnasconi, NXP.
Listen to panel >

Technical Excellence Award Presented

Congratulations Tom Fitzpatrick, recipient of the 2019 Accellera Technical Excellence Award! Tom is a noted verification evangelist and is being honored for his many years of dedication to the advancement of Accellera standards. He has been a key contributor to the evolution and adoption of the Universal Verification Methodology (UVM) standard, Verilog and SystemVerilog standards and the development and launch of the Portable Test and Stimulus Standard 1.0 (PSS).

The award was established to recognize the outstanding achievements of an individual among Accellera’s working group members and their significant contributions to the development of its standards. Find out more >