PSS 2.0 Draft Standard Open for Public Review

The Portable Test and Stimulus Draft Standard 2.0 (PSS) is now available for public review. Download the draft standard for review here.

The Portable Test and Stimulus Draft Standard 2.0 includes about 90% of the projected functionality that will be included in the official Portable Test and Stimulus Standard 2.0 release expected in March 2021. New major features intend to improve the usability of the Portable Test and Stimulus Standard 2.0 and expand its portability and flexibility to a broader class of verification challenges. For more details, read the press release. 

Public review runs from November 18, 2020 to December 18, 2020.

Accellera’s Portable Stimulus Working Group (PSWG) welcomes feedback from the community on the major additions included in the draft while the group finalizes the remaining functionality. Feedback can be provided through Accellera’s Portable Stimulus 2.0 Public Review Community Forum.

Accellera Day Videos from DVCon U.S. 2020 Available!

Tutorial: Portable Stimulus: What's Coming in 1.1 and What it Means for You
This technical tutorial provides an overview of the proposed PSS 1.1 standard. Presenters review the basic modeling constructs, use model and test realization specifications in a PSS verification intent model and show the enhanced capabilities being implemented for 1.1. View the tutorial >

Luncheon Panel focused on the Portable Stimulus Standard
As a follow-up to the tutorial on the Portable Stimulus Standard (PSS), attendees were given the opportunity to interact with members of the Portable Stimulus Working Group and ask their most pressing questions. Listen to the panel discussion >

Short Workshop: An Introduction to the Emerging IP Security Assurance Standard
The workshop, presented by members of the IP Security Assurance Working Group focuses on: Methodology, detailing the overall concept and workflow along with the individual components, dependencies, and assumptions; Security weakness knowledge base, highlighting potential IP security concerns; OpenCores examples to demonstrate how the methodology applies to real IP cores; Summary and outlook, providing the road map and expectations moving forward. View the workshop >

Short Workshop: How HLS and SystemC is Delivering on its Promise of Design and Verification Productivity
The workshop begins with an introduction to the SystemC Synthesizable Subset and an introduction to basic concepts of how HLS works to go from a SystemC/C++ description to quality RTL. Real-world use-cases and the results achieved are presented by Intel and NVIDIA. View the workshop >