Media Coverage
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2019 |
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| September 13th | DVCon U.S. Serves Chip Users Latest Tools and Standards Semiconductor Digest |
| August 19th | How Do We Tackle Chip Security? EEJournal |
| July 22nd | DVCon U.S. Serves Chip Users Latest Tools and Standards ChipEstimate |
| June 25th | Tales from DAC: A Meeting of Security's Heroes at the Accellera Luncheon (Part 2 of 2) Cadence Functional Verification Blogs |
| June 24th | Tales from DAC: A Meeting of Security's Heroes at the Accellera Luncheon (Part 1 of 2) Cadence Functional Verification Blogs |
| June 4th | Accellera’s Chair Discusses Value of Membership EDACafe |
| June 4th | The Unknown Unknowns of Secure Devices Tech Design Forum |
| June 4th | DAC 2019: Day 1 Semiconductor Engineering |
| May 26th | Semiconductor IP Security Issues SemiWiki |
| March 19th | Accellera Begins IP Security-Assurance Standards Effort Tech Design Forum |
2018 |
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| October 4th | Accellera Tackles IP Security SemiWiki |
| August 8th | Agile Standards Semiconductor Engineering |
| July 6th | EDA Embraces Standard to Streamline IC Test and Verification Electronics Weekly |
| July 2nd | Tools Suppliers Back Version 1.0 of Portable Stimulus Standard Tech Design Forum |
| February 1st | DVCon US 2018 is Bigger and Better EDACafe |
2017 |
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| October 17th | Developing the Portable Stimulus Standard Chip Design |
| August 24th | Portable Stimulus Status Report Semiconductor Engineering |
| March 12th | Celebrating Accellera’s UVM: Now it’s IEEE 1800.2 EDACafe |
| April 27th | Lu Dai: Incoming Accellera Chair SemiWiki |
| February 23rd | Qualcomm’s Lu Dai: Energetic leadership for Accellera EDACafe |
2016 |
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| August 15th | Accellera Relicenses SystemC Reference Implementation under the Apache 2.0 License Gabe's EDA |
| July 14th | Shishpal Rawat: Intel, CEDA, Accellera, Calm Commitment EDACafe |
| March 29th | Specs vs. Implementation; Portable Stimulus; Hardware-Software Differences JB Systems |
| March 3rd | Prove It! The New Era of Design Verification Amelia's Weekly Fish Fry |
| January 2016 | SystemVerilog, a Global Success Story, Celebrates 10 Years Speeding Technology to Market IEEE-SA Standards Focus |
2015 |
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| Summer 2015 | Designing Efficiently for a Low Power World EDACafe |
| March 5th | DVCon: The Imitation Game EDACafe |
| February 11th | Accellera Systems Initiative Forms Portable Stimulus Working Group Electronic Engineering Journal |
| February 11th | Accellera Adds Portable Stimulus Group Semiconductor Engineering |
2014 |
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| September 25th | Intel's Shishpal Rawat: Multiple hats, Singular focus EDACafe |
| July 1st | Accellera Updates UVM Standard Semiconductor Engineering |
| June 3rd | Accellera Enhances Mixed-signal Modeling and Verification in Verilog-AMS 2.4 Standard Low-Power Design |
2013 |
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| March 20th | Accellera publishes SystemC-AMS 2.0 standard Tech Design Forum |
| February 25th | DVCon 2013: Engineers Question EDA Standards Leaders at Accellera "Town Hall" Meeting Cadence Industry Insights Blog |
| February 6th | Master & Commander: DVCon's Stan Krolikoski EDACafe |