Media Coverage

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2022
January 11th Video: Pre-silicon D&V innovation and standardization efforts from Accellera
EDACafe Bunker Broadcast

2021
December 14th DAC 2021 – Accellera Panel all about Functional Safety Standards
SemiWiki
December 9th Design rules for functional safety are explored at DAC
Electronics Weekly
September 8th Functional Safety Working Group
Semiconductor Engineering
August 11th Challenges of Transitioning Back from Remote Work to Office
Pradeep's Techpoints
July 21st A Hardware Security Standard Advances
SemiWiki
June 23rd 5 Verification Engineers Provide Tips to Succeed When Working From Home
Design News
June 9th How easy is it building chips during a pandemic?
Pradeep's TechPoints
May 27th Accellera Unveils PSS 2.0 – Production Ready
SemiWiki
May 26th Functional Safety – What and How
SemiWiki
May 11th Accellera’s Functional Safety Group White Paper
Semiconductor Engineering
April 8th Interconnects In A Domain-Specific World
Semiconductor Engineering

2020
December 17th An Accellera Update. COVID Accelerates Progress
SemiWiki
October 14th IP Security Assurance Standard
Semiconductor Engineering
August 6th Accellera Tackles Functional Safety
Semiconductor Engineering
July 23rd Accellera IP Security Group Expects Standard by Year End
Tech Design Forum
July 10th Accellera’s Chair Highlights 2020 Events & Working Group Activity
EDACafe, Video Interview
May 5th Accellera Tackles Functional Safety, Mixed-Signal
SemiWiki
April 14th What is the Difference Between Test and Verification?
Design News
March 26th Standard Evolution
Semiconductor Engineering
March 26th Do You Trust Your IP Supplier?
Semiconductor Engineering
March 20th Create Once and Test Everywhere: The Promise of Portable Stimulus
Design News

2019
December 30th Silicon IP Security Proposal
EEJournal
November 13th Functional Safety Comes to EDA and IP
SemiWiki
November 1st Plotting a Course to Functional Safety
Amelia's Weekly Fish Fry
October 10th Accellera IP Security Standard: A Start
SemiWiki
September 13th DVCon U.S. Serves Chip Users Latest Tools and Standards
Semiconductor Digest
August 19th How Do We Tackle Chip Security?
EEJournal
July 22nd DVCon U.S. Serves Chip Users Latest Tools and Standards
ChipEstimate
June 25th Tales from DAC: A Meeting of Security's Heroes at the Accellera Luncheon (Part 2 of 2)
Cadence Functional Verification Blogs
June 24th Tales from DAC: A Meeting of Security's Heroes at the Accellera Luncheon (Part 1 of 2)
Cadence Functional Verification Blogs
June 4th Accellera’s Chair Discusses Value of Membership
EDACafe
June 4th The Unknown Unknowns of Secure Devices
Tech Design Forum
June 4th DAC 2019: Day 1
Semiconductor Engineering
May 26th Semiconductor IP Security Issues
SemiWiki
March 19th Accellera Begins IP Security-Assurance Standards Effort
Tech Design Forum

2018
October 4th Accellera Tackles IP Security
SemiWiki
August 8th Agile Standards
Semiconductor Engineering
July 6th EDA Embraces Standard to Streamline IC Test and Verification
Electronics Weekly
July 2nd Tools Suppliers Back Version 1.0 of Portable Stimulus Standard
Tech Design Forum
February 1st DVCon US 2018 is Bigger and Better
EDACafe

2017
October 17th Developing the Portable Stimulus Standard
Chip Design
August 24th Portable Stimulus Status Report
Semiconductor Engineering
March 12th Celebrating Accellera’s UVM: Now it’s IEEE 1800.2
EDACafe
April 27th Lu Dai: Incoming Accellera Chair
SemiWiki
February 23rd Qualcomm’s Lu Dai: Energetic leadership for Accellera
EDACafe

2016
August 15th Accellera Relicenses SystemC Reference Implementation under the Apache 2.0 License
Gabe's EDA
July 14th Shishpal Rawat: Intel, CEDA, Accellera, Calm Commitment
EDACafe
March 29th Specs vs. Implementation; Portable Stimulus; Hardware-Software Differences
JB Systems
March 3rd Prove It! The New Era of Design Verification
Amelia's Weekly Fish Fry
January 2016 SystemVerilog, a Global Success Story, Celebrates 10 Years Speeding Technology to Market
IEEE-SA Standards Focus

2015
Summer 2015 Designing Efficiently for a Low Power World
EDACafe
March 5th DVCon: The Imitation Game
EDACafe
February 11th Accellera Systems Initiative Forms Portable Stimulus Working Group
Electronic Engineering Journal
February 11th Accellera Adds Portable Stimulus Group
Semiconductor Engineering

2014
September 25th Intel's Shishpal Rawat: Multiple hats, Singular focus
EDACafe
July 1st Accellera Updates UVM Standard
Semiconductor Engineering
June 3rd Accellera Enhances Mixed-signal Modeling and Verification in Verilog-AMS 2.4 Standard
Low-Power Design

2013
March 20th Accellera publishes SystemC-AMS 2.0 standard
Tech Design Forum
February 25th DVCon 2013: Engineers Question EDA Standards Leaders at Accellera "Town Hall" Meeting
Cadence Industry Insights Blog
February 6th Master & Commander: DVCon's Stan Krolikoski
EDACafe

2012
December 13th A look back on 2012: Accellera
EE Times
July 18th Accellera Systems rolls new SystemC Library
EDN Asia
July 18th Accellera Systems Initiative: team effort & SystemC Library 2.3
EDACafe
June 11th DAC 2012: How Unified Coverage Interoperability Standard (UCIS) Will Ease IC Verification
Cadence: Industry Insights
February 28th European SystemC User's Group - Interview with Axel Braun
TLM Central
February 21st DVCon 2012 Insider: Tech. Papers, Tutorials, Keynote, Industry Leaders Panel and Accellera Systems Initiative", Karen Bartleson, Gen. Chair DVCon2012
EDACafe
January 30th Top 10 Tips for Success with Formal Analysis - Part 2
EE Times
January 17th Accellera puts next release of SystemC library up for review
ElectronicsWeekly
January 16th Accellera Systems Initiative Announces Call for Nominations for 2012 Technical Excellence Award for EDA and IP Standards Contributions
EDACafe
January 6th EDA standards bodies Accellera, OSCI merge [Chinese]
EETimes Taiwan
January 5th EDA Standards and Accellera Systems Initiative [Japanese]
Semiconductor Portal