Community Newsletter: February 2025


IN THIS ISSUE:

 

Message from the Chair

Lu Dai, Accellera Systems Initiative ChairHappy New Year! As we step into 2025, Accellera is gearing up for an exciting year filled with standards developments, global events, and important discussions that will help shape the future of our industry.

We are pleased to announce that the Accellera Board of Directors has approved the Universal Verification Methodology for Mixed-Signal (UVM-MS) 1.0 standard for immediate release. This much-anticipated standard will significantly enhance the verification of AMS products and applications, and we look forward to its positive impact on the industry.

In other key developments:

  • The Federated Simulation Standard Working Group has issued a Call for Contributions. If you are interested in helping to shape the development of the standard itself or contributing technologies to develop the ecosystem, please get in touch.
  • The Clock Domain Crossing Working Group is gearing up for another round of public review for feedback.
  • The SystemVerilog Mixed-Signal Interface team is nearing completion of its 1.0 standard.

Accellera will also have a strong presence at industry events worldwide, including our six sponsored DVCon conferences in the US, Europe, India, China, Japan, and Taiwan. We're also hosting a luncheon at the 62nd annual Design Automation Conference on June 24 in San Francisco, California, as well as the annual SystemC Evolution Day co-located with DVCon Europe in October in Munich.

No matter where you are, there's an Accellera event near you offering opportunities to connect, learn, and contribute to the evolution of standards to improve design and verification productivity.

As technology evolves, we continue to explore new and growing challenges such as:

  • Higher Abstraction
    System-level design and chiplets are not new concepts, but their adoption is accelerating. What can we do as a community to further advance interoperability and efficiency in these areas?
  • Security in Design & Verification
    With increasing geopolitical challenges and the growing sophistication of cyber threats, security is more critical than ever. How do we balance security with efficiency and legal obligations such as public disclosure of vulnerabilities? How can standards help ensure secure design practices?
  • AI & its Impact
    Artificial Intelligence is reshaping our industry—from AI-driven EDA algorithms to data sharing, security concerns, and the increasing complexity of semiconductor designs. Should we be working toward common data formats? What new challenges and opportunities will AI bring to design and verification?

Accellera welcomes your ideas and collaboration. As we move forward in 2025, we invite you to share your thoughts on these or other important topics. Whether through participation in our working groups, discussions at industry events, or contributions to evolving standards, your insights are valuable in shaping the future.

Sincerely,
Lu Dai, Accellera Systems Initiative Chair

 

News from Accellera Working Groups

UVM-MS 1.0 Now Available!

UVM-MS (Mixed-Signal) logo

The Accellera Board of Directors has approved the Universal Verification Methodology for Mixed-Signal (UVM-MS) 1.0 standard for release. The new standard is available for immediate download fee-free.

The UVM-MS 1.0 standard is a comprehensive and unified analog/mixed-signal (AMS) verification methodology based on the UVM IEEE Std. 1800.2™. This standard significantly enhances the verification of AMS and digital/mixed-signal (DMS) integrated circuits and systems. It defines a robust framework that facilitates the creation of AMS verification components and testbenches by extending digital-centric UVM classes and enabling interaction between class-based and structural environments.

"I'd like to congratulate the members of the UVM-MS Working Group for their dedication and hard work in delivering this much-anticipated standard that will significantly enhance the verification of AMS products and applications," stated Lu Dai, Chair of Accellera. "The strong industry interest in this standard underscores its importance. As an organization devoted to improving design and verification productivity for both users and vendors, we eagerly anticipate its positive impact on the industry.

Read the full UVM-MS press release. For more information, visit the UVM-MS Working Group page.

Federated Simulation Standard WG Issues Call for Technology Contributions

Accellera's Federated Simulation Standard (FSS) Working Group and User Group, launched in 2024, aim to develop a standard and open infrastructure to enable interoperability among established modeling and simulation standards, technologies, and tools as part of a distributed, orchestrated simulation ecosystem.

Since its inception, the working group and user group have defined the objectives for standardization and identified key use cases and application scenarios. Based on these objectives, the working group announced its Call for Technology Contributions in January 2025. Organizations are invited to contribute proposals for the development of the standard itself or contribute technologies to develop the ecosystem.

The Call for Technology Contributions is open through February 28, 2025. Contact Accellera for details about the submission process and opportunities to participate in the development of the Federated Simulation Standard and its implementation.

You will find more information about the working group on the Federated Simulation Standard Working Group page.  

New Video from the Functional Safety Working Group Now Available

The Functional Safety Working Group presented a workshop during DVCon U.S. 2024 focused on the development of the data model and whitepaper as well as an example of the Functional Safety standard. View the Functional Safety Working Group video here.

The charter of the Functional Safety Working Group is to focus on the standardization of the functional safety intent data model/format to improve interoperability and traceability in the functional safety lifecycle. The aim is to provide a unified approach throughout the product creation process, specifically to enable a functional safety-aware design and verification flow for electronic circuits and systems.

For more information about the working group, visit the Functional Safety Working Group page.

 

Accellera at DVCon U.S. 2025

DVCon U.S. 2025 logoWe hope to see you during DVCon U.S. February 24-27 in San Jose, California where we'll have five informative workshops presented by our working group leaders. We'll also have a luncheon presentation featuring the latest Accellera updates, the presentation of the prestigious Technical Excellence Award, and an overview of our newest standard.

The following Accellera-sponsored DVCon events are open to registered DVCon attendees (these events are not part of the free registration option).

IEEE 1801-2024 Workshop

"Introduction of IEEE 1801-2024 (UPF 4.0)"

Monday, February 24 | 9:00-10:30am

This workshop will explore the key advancements in the IEEE 1801-2024 (UPF 4.0) standard, designed to address the growing complexity of modern low-power architectures. Attendees will gain insights into the new methodologies for verification, implementation, and reuse of power intent specifications that are critical for flexible IP design, analog-digital interfaces, and state retention modeling.

Universal Verification Methodology (UVM) Workshop

"Moving Forward with IEEE 1800.2 UVM: Practical Insights and the Benefits of Migration"

Monday, February 24 | 11:00-12:30pm

This workshop highlights the latest enhancements in the IEEE 1800.2 UVM standard, as introduced in Accellera's reference implementation (2020.3.1). It offers practical guidance for verification engineers, focusing on performance improvements, functional updates, and strategies for a smooth migration from UVM 1.2.

Accellera Luncheon

Join Accellera for Lunch!

Monday, February 24 | 12:30-1:30

  • Accellera Update and Look to the Future presented by Lu Dai, Accellera Chair
  • Accellera Technical Excellence Award Presentation
  • Introduction to the UVM-MS 1.0 standard

Portable Stimulus Workshop

"PSS Comes of Age: Runtime Behavioral Coverage, Methodology and More"

Monday, February 24 | 3:30-5:00

This workshop will dive into the key advancements in the Portable Stimulus Standard (PSS) 3.0 and ongoing efforts by the working group, highlighting the language's evolution and maturity. Attendees will gain a deeper understanding of PSS 3.0's capabilities and the tools available to streamline portable stimulus test creation and implementation.

IP-XACT Workshop

"SoC Development Automation using IP-XACT 1685-2022 Standard"

Thursday, February 27 | 9:00-10:30

This workshop explores the complexities of the SoC development process and highlights how the IEEE IP-XACT 1685-2022 standard streamlines workflows, fosters standardization, and enables automation. Attendees will gain insights into optimizing SoC development by standardizing processes and integrating automation with IP-XACT.

Clock Domain Crossing (CDC) Workshop

"CDC/RDC Interchange Format Standard"

Thursday, February 27 | 11:00-12:30

This workshop highlights the critical role of Clock Domain Crossing and Reset Domain Crossing (RDC) analysis in modern SoC development, addressing challenges posed by increasing design complexity and diverse verification tool ecosystems. Attendees will learn how standardization can enhance quality and efficiency in CDC-RDC analysis for advanced SoC designs.

 

Upcoming Events

DVCon U.S. 2025

DVCon U.S. 2025 logoThe 37th annual DVCon U.S. will be held February 24-27, 2025, at the Doubletree Hotel in San Jose, California. The conference program offers attendees a wide selection of workshops, tutorials, posters, technical papers and exhibits to choose from.

"I am particularly excited about the engaging keynotes and panel topics we've lined up for attendees this year," said Tom Fitzpatrick, DVCon U.S. 2025 General Chair. "Each topic is not only compelling, but also relevant to the challenges and opportunities our industry faces today."

Attendees will have the opportunity to hear from two keynote sessions:

  • Tuesday keynote: Ravi Subramanian, General Manager of the Systems Design Group at Synopsys, and Artour Levin, Vice President of AI Silicon Engineering at Microsoft, will share their insights on how the "AI-driven Era of Pervasive Intelligence Necessitates New Design, Optimization, and Verification Strategies."
  • Wednesday Invited Keynote: Rob Aitken, a seasoned EDA veteran and current Program Manager at the National Advanced Packaging Manufacturing Program under the CHIPS for America initiative, will deliver a talk on "The Role of EDA in U.S. Economic Security." His presentation will focus on the broader impact of the EDA industry, highlighting how its advancements and individual contributions extend well beyond delivering the next chip.

Wednesday morning's panel will explore the critical question, "Are AI Chips Harder to Verify?" This discussion will bring together industry luminaries who will share their insights on a range of topics, from adapting traditional verification techniques for these complex systems to leveraging AI-assisted approaches to streamline the verification process. The session will be moderated by Moshe Zalcberg, CEO of Veriest Solutions, helping to ensure a thought-provoking and dynamic exchange of ideas.

For a complete program schedule and registration information, visit the DVCon U.S. 2025 website. Registration for the keynotes, panel, and exhibits is free.

DVCon China 2025

DVCon China 2025 logoDVCon China will be held April 16 at the Shanghai Renaissance Pudong Hotel.

Welcome Message from DVCon China 2025 General Chair

Dear attendees and colleagues,

Welcome to the 2025 DVCon China Conference! As the chair of this conference, l am truly honored to be here with all of you. lt's exciting to gather together and discuss the latest trends and cutting-edge technologies in the field of design verification. [This seems too "right now" for the newsletter. I'd like to delete it]

In recent years, we've seen tremendous growth in China's chip development across various sectors, particularly in critical areas like CPUs, GPUs, artificial intelligence, automotive electronics, communications, and the Internet of Things (loT). lt's inspiring to witness the rapid rise of domestic companies in these fields, which not only drives technological advancement but also enhances our overall market competitiveness.

As we continue to accelerate chip development, our community of design verification engineers is expanding at an impressive pace. More talented engineers are joining our ranks, bringing fresh perspectives and innovations that are vital to our industry's progress. Design verification is not just about ensuring product quality; it's also key to improving our overall research and development efficiency.

While we strive for speed and efficiency, we must also emphasize creativity and innovation. Whether it's through developing new tools and processes or creatively solving challenges in our engineering projects, the contributions of design verification engineers are crucial. lt's through our commitment to continuous innovation that we can stay competitive in this fast-paced market.

Every year, the DVCon China Conference attracts hundreds of engineers from leading companies across the country. This gathering is not only about learning and sharing knowledge, but it's also a fantastic opportunity to connect and network with fellow professionals. l encourage you to take advantage of this platform to explore the latest features of lC tools, discover new solutions, and make new friends in the industry. l hope you leave this [I'd like to change this to "the"]conference with valuable insights that will benefit you both technically and personally.

Thank you all for being here, and [I's like to remove this part]l look forward to an enriching and exciting conference experience together!

Thank you!
Bin Liu
DVCon China 2025 General Chair

For more information on the conference, including registration information, visit the DVCon China 2025 website.

62nd Annual Design Automation Conference

DAC 2025 logoSave the date! Accellera is excited to invite you to our hosted luncheon on Tuesday, June 24, at the 62nd annual Design Automation Conference in San Francisco, California. The luncheon will take place at Moscone West in Room 3016. We are planning an engaging session where we will delve into a cutting-edge topic with industry-leading speakers. Details on the topic and speakers will be announced closer to the event. Stay tuned for more information in the coming weeks. Visit the Accellera Events Page for the most up-to-date information.

More Upcoming Events

For more information on Accellera events planned throughout 2025, visit the Accellera Events page. Since we just said this above in the DAC paragraph, I'd like to remove it here]

 

Stanley J. Krolikoski Scholarship Now Open for Applications

Accellera is now accepting applications for its 2025 scholarship for Electrical Engineering and Computer Science Students. The scholarship was established in 2022 to honor long-time Accellera friend and colleague Stan Krolikoski. Applications for the $1,500 scholarship will be accepted through April 30, 2025.

For more information and to submit your application, visit the Accellera Scholarship page.

 

Follow Accellera on YouTube

Check out Accellera's official YouTube channel where you can find the latest videos from our working groups, industry events, and technical presentations.

In addition to YouTube, we also host a rich collection of videos on our Vimeo channel. Be sure to check out both platforms to explore content that interests you.

 

Explore the DVCon Archives

For papers, posters, presentations and videos from our DVCon conferences around the globe, visit the DVCon archive site.

 

Recent Press Coverage

Bob Smith, Executive Director at ESD Alliance, and Accellera Chair Lu Dai recently discussed what's new at Accellera, upcoming conferences, and much more. Read the blog "Checking in on Accellera's Industry Standards Efforts and Global Reach" posted in Semi.org.

Daniel Payne, editor for SemiWiki.com, looks at recent activity in the SystemC ecosystem, including recent events, standards updates, and news from our SystemC working groups. See what he as to say in his "SystemC Update 2024" article.

 

IEEE Get Program Update

Since its inception, the Accellera-sponsored IEEE Get Program has resulted in over 200,000 downloads. The IEEE Get Program provides no cost access of electronic design and verification standards to engineers and chip designers worldwide. For more information and to view the standards available for download, visit the Available IEC/IEEE Standards page on the Accellera website.

 

Accellera Global Sponsors

CadenceSiemens EDASynopsys

Contact us if you are interested in becoming a Global Sponsor.

 

Copyright 2025 Accellera Systems Initiative