Community Newsletter: December 2023
IN THIS ISSUE:
- Message from the Chair
- Working Group Updates
- New Functional Safety Whitepaper
- Clock Domain Crossing Draft Standard 0.1 Public Review
- SystemC 3.0.0 Public Review
- PSS 2.1 Available for Download
- IEEE 1666-2023 Available in GET Program
- Federated Simulation Standard Proposed Working Group Update
- Recent Press Coverage
- Semiconductor Engineering: “What Happened to Portable Stimulus?”
- Semiconductor Engineering: “Anatomy of a System Simulation”
- EE News Europe: “EDA Standards for AI/China”
- DVCon U.S. 2024 Registration Open
- Recent 2023 Events Wrap-up
- DVCon Europe
- SystemC Evolution Day
- DVCon China
- DVCon India
- DVCon Taiwan
- SystemC Fika
- IEEE Get Program Update
I’d like to begin by congratulating the DVCon Europe team on its 10th year of the conference. Held in Munich last month, there were many interesting technical presentations, engaging panel discussions, and thought-provoking keynote speakers. A highlight enjoyed by all was the evening celebration where engineers gathered to raise a toast amidst the sounds of the Beatles and Queen, with lyrics reimagined to focus on DVCon Europe’s milestone birthday.
In addition to our DVCon Conferences in Europe and the U.S., we have expanded our reach with four conferences serving communities throughout Asia. DVCon Taiwan, the latest addition, joins established conferences in India, Japan, and China. The inaugural conference in Taiwan, held in September, drew a sizeable audience eager to learn more about design and verification solutions and standards.
While our conferences serve as platforms to learn about existing standards, Accellera continues to explore possibilities for new standards beneficial to our industry. We recently announced the Federated Simulation Standard Proposed Working Group (PWG), aiming to bridge the gap across various simulation platforms in different industries. This represents a significant challenge over Accellera’s traditional focus on multiple languages across multiple vendors within our industry. The PWG welcomes your input and participation in this very crucial new initiative.
With the rapid emergence of AI, the focus on supply chain security and the increase in discussions surrounding chiplet technology, there are tremendous opportunities for us to apply our expertise to standardization efforts in these areas. As always, we encourage your ideas and leadership in exploring these new frontiers.
Exciting news from our working groups also deserves mention: Our Functional Safety Working Group has just released its second whitepaper, the Clock Domain Crossing Working Group’s 0.1 Draft Standard is available for public review through December 31st, and the Portable Test and Stimulus Standard 2.1 has been released for download.
As the holidays approach and 2023 draws to a close, I’d like to extend warm wishes to all of our members worldwide. May your days be filled with coding joy and standards-driven happiness.
I wish you a very happy new year.
Lu Dai, Accellera Systems Initiative Chair
Hot Off the Press! New Functional Safety Whitepaper Available
The Functional Safety Working Group has just released its second whitepaper with a focus on the data model. The data model is intended to support the generation and interchange of functional safety content that represents diverse elements of the safety cases of safety-relevant systems, modules, components, and IP in related industries. The data model is a foundational component to complete the working group objectives defined in the Functional Safety Working Group White Paper that was released in 2021.
The goal and scope of the data model is to capture and propagate the functional safety content across the different safety operations and the distributed development environment, from system to IPs. Achieving this goal will enable automation, interoperability, and traceability across safety activities. Download the whitepaper here.
For more information on the working group, including a list of resources, visit the Functional Safety Working Group page.
The Clock Domain Crossing (CDC) Working Group recently announced the availability of its Draft Standard 0.1 for public review. The draft standard can be downloaded here.
The working group invites the community to provide feedback through its Community Forum. The public review is open through December 31, 2023.
The CDC Working Group was formed to define a standard CDC collateral specification to ease SOC integration. In-house and externally purchased IPs are often combined in SOCs. It can prove challenging to verify these SOCs because a mixture of verification tools and methodologies that do not integrate are sometimes used. Ensuring that a common clock domain crossing interface standard that every tool can translate their native format to and from is the intent of this standard. With this interface standard, every IP developer’s verification tool of choice is run to verify and produce collateral, and the standard format is generated for SOCs that used a different tool. With this CDC standard, efficiently translating from provided collateral into a tool of choice is possible for every SOC.
This standard is intended to do the following:
- Enable all EDA vendors to develop tools that meet this specification in generated collateral
- Enable IP companies to generate collateral using various vendors and their tools
- Enable SOC companies to consume generated collateral from different vendors’ tools into their tool of choice
For more information on the working group, visit the Clock Domain Crossing Working Group page.
The SystemC reference implementation version 3.0.0 has been released for public review through January 19, 2024. This version of the library is fully compatible with the IEEE Std 1666-2023 SystemC Language Reference Manual.
- Based on C++17 (ISO/IEC 14882:2017)
- Introduction of simulation stage callbacks
- Possibility to suspend/unsuspend the simulation kernel to enable interaction with external threads
- Improved simulation performance for big-integer data types
- Time resolution down to yoctoseconds (10−24)
- Many minor enhancements to improve SystemC modeling style and usage
For more information on SystemC 3.0.0, including a list of what’s new, you can view the release notes here.
For more information on the SystemC standard, visit the SystemC Community Portal.
The Portable Test and Stimulus Standard (PSS) 2.1 is now available for download.
“I am very proud of our dedicated working group members as we continue to develop the standard and bring even more flexibility and new capabilities to our user community,” stated Tom Fitzpatrick, Vice Chair of the Portable Stimulus Working Group. “We have made significant advances with PSS 2.1, including new features that collectively enhance the versatility and efficiency of PSS to advance and simplify modern electronic system verification. We welcome feedback from the community as we continue to develop the standard.”
PSS defines a means to create a single representation of stimulus and test scenarios, usable by a variety of users across many levels of integration under different configurations. This representation facilitates the generation of diverse implementations of scenarios that run on a variety of execution platforms, including simulation, emulation, FPGA prototyping, and post-silicon. With this standard, users can specify intent once and observe consistent behavior across multiple implementations.
The update to the standard focuses on modeling and usability, with the introduction of many significant features aimed at enhancing the standard’s capabilities for efficient hardware and software verification.
These additions include:
- Support for floating-point data types and associated math functions, which broaden the scope of verifiable designs
- Enhanced capabilities for interaction with memory management via features for implementing custom address translation and querying the source address region of allocated memory
- Enabling more flexible generation of random data via support for randomizing the contents of lists, performing constrained randomization in exec blocks and functions, and specifying distribution weights
- Providing core library support for emitting formatted text and messages, operating on files, and error reporting
Accellera recently announced that the IEEE 1666™-2023 Standard for SystemC Language Reference Manual (LRM) is now available for download fee-free, courtesy of Accellera as part of the IEEE GET Program.
"Our close partnership with the IEEE Standards Association is a tremendous benefit to design and verification engineers around the globe,” stated Lu Dai, Accellera Chair. “SystemC has been in use for more than two decades, and as the standard is revised, Accellera will continue to leverage its relationship to provide SystemC and other much-needed standards to the community fee-free.”
SystemC addresses the need for a system design and verification language that spans hardware and software. It is a language built in standard C++ by extending the language with the use of class libraries. The language is widely used for Digital Twins in the semiconductor space, allowing early embedded software development and effective hardware/software codesign.
“The 2023 revision builds on enhancements and new features contributed by the SystemC community during the last decade,” stated Jerome Cornet, IEEE 1666™ Working Group Chair. “More than fifty topics in over ten categories have been considered by the working group. This revision provides a new C++ baseline leveraging a mature ISO C++ version, numerous enhancements, and key new capabilities, notably for communicating with other simulations, such as simulation stage callbacks or the suspend mechanism.
For more information about SystemC, including a list of resources and upcoming events, visit the SystemC Community Portal.
The IEEE GET Program was established in 2010 to provide pre-paid access of selected standards to engineers and designers worldwide at no cost. The program helps expand the global reach of technical knowledge developed by industry, accelerates standards adoption, and contributes to an open knowledge community and the fostering of innovation. As a partner in the GET Program since its inception, Accellera has sponsored more than 175,000 downloads of Accellera-developed standards. For a list of Accellera and IEEE standards available for download at no cost, visit the Accellera Downloads page.
Federated Simulation Standard Proposed Working Group Update
Accellera recently announced the formation of a Federated Simulation Standard Proposed Working Group (PWG) to identify industry interest in developing a standardized communication interface to enable interoperability of virtual modeling, simulation, and integration throughout the product lifecycle. The intent of this communication standard is to facilitate the creation of a distributed and orchestrated (“federated”) multi-domain simulation framework, compatible with and complementary to existing approaches used in different industries and sectors.
The PWG has been meeting regularly. If you’d like to participate and are an Accellera member, you can join the PWG here (login required). If you are not an Accellera member and would like to participate in the PWG, submit your information here.
Brian Bailey, Semiconductor Engineering, talks with Tom Fitzpatrick, Portable Stimulus Working Group Vice Chair, for the article “What Happened to Portable Stimulus?” It’s an interesting read that describes the standard, how it’s being adopted throughout the industry, and what lies ahead.
Semiconductor Engineering’s “Anatomy of a System Simulation” touches on the Accellera Federated Simulation Standard Proposed Working Group (FSS PWG). For input, Brian Bailey talks with Martin Barnasconi, FSS PWG Chair, and Mark Burton, FSS PWG Vice Chair.
Nick Flaherty, EE News Europe, talks with Lu Dai, Accellera Chair, for “EDA Standards for AI, China.”
The 36th annual DVCon U.S. will be held March 4-7, 2024, at the Doubletree Hotel in San Jose, California. Registration is open and the advance program will be available soon. Visit the website for the most up-to-date information.
DVCon is the premier conference on the application of languages, tools, methodologies, and standards for the design and verification of electronic systems and integrated circuits. The focus of the technical conference and exhibition is educating attendees about the practical aspects of these technologies and their use in leading-edge projects to help improve their own design and verification flows.
For inspiration, the proceedings from DVCon U.S. 2023 are available to view on demand.
“I am pleased and proud to celebrate our 10th anniversary with our engineering community from around the world,” commented Martin Barnasconi, DVCon Europe General Chair. “The addition of the new research track truly enriched the technical program and attracted a lot of interest. We had participation from 181 different affiliations and 20 exhibitors for attendees to visit. We also had presentations and discussions on AI, high-performance compute, and chiplets. Design, verification, and system-level design continue to be of growing interest, with even more papers in this year’s program than previous years.”
The Best Paper Award in the engineering category went to “The Three Body Problem: There’s More to Building Silicon than EDA Tools Currently Help,” by Peter Birch, VyperCore, and Ben Marshall, PQShield. In the Research category, Best Paper was won by “Clock Tree Design Considerations in the Presence of Asymmetric Transistor Aging,” by Freddy Gabbay PhD, Ruppin Academic Center, Israel, and Firas Ramadan and Majd Ganaiem of Technion - Israel Institute of Technology.
DVCon Europe 2024 will be held in Munich October 15-16, followed by SystemC Evolution Day on October 17.
The “Future of SystemC” was the theme of this year’s SystemC Evolution Day, co-located with DVCon Europe on November 16. Presenters throughout the day took the opportunity to reflect on the status of the SystemC standard and library implementation and discuss what should happen next. Attendees and presenters alike recognize that there are great opportunities to further evolve the standard, especially as it relates to the larger systems-of-systems ecosystem.
The big news at the event was around the forthcoming SystemC 3.0 proof of concept simulator, the public review for which will start shortly. Details were given about the implementation and the various improvements in the code. The review will take place on the public GIT repository and everybody is welcome to contribute.
As well as a fruitful discussion on introspection, there was also a deep dive into how to connect simulators — one of the most challenging problems currently facing the industry. In this context, Accellera’s Federated Simulation Standard Proposed Working Group was discussed — how it could affect SystemC and how SystemC could be of help to the potential standard.
“It was truly an exciting day having the community come together to discuss the future of the SystemC standard,” stated Mark Burton, SystemC Evolution Day Chair. “Attendees were treated to a great user story focused on RISC-V simulation and how SystemC can be used to simulate relatively complex and complete systems. The day concluded with an in-depth discussion about how to improve the CCI library, which will be a very important project. We hope you’ll join us in helping to evolve the standard and make a difference.”
For more information on SystemC and upcoming events, visit the SystemC Community Portal.
The third DVCon China was held in Shanghai in September. The full-day conference offered attendees 12 technical papers, nine workshops, two tutorials, and two keynotes. The keynotes, “CEDA 2.0 – Leveraging AI to Achieve the Next 10X” presented by Yogesh Goel, Cadence, and “System Design with Agile Verification and Continuous Acceleration” presented by Felix Cha, XEPIC, were well attended and offered attendees thought-provoking presentations.
For more information on DVCon China and the latest updates on the conference schedule, visit the conference website.
The eighth annual DVCon India was held over two days in September, offering attendees an extensive technical program and exhibition. There were six keynotes on high-level industry topics; eight workshops, including one presented by Accellera Chair, Lu Dai; two panels; 16 poster sessions; a vision talk; and numerous tutorials to choose from. Nearly 1,000 participants, including 495 students, attended the conference.
This year the DVCon India Steering Committee presented its first Lifetime Achievement Award to Nilesh M Desai, ISRO. There were many other awards presented during the conference, including Design Contest, Best Paper and Best Poster winners. For the complete list of recipients, visit the website.
Save the date! DVCon India 2024 will be held in Bangalore September 18-19. For the most recent information on the conference, visit the website.
For proceedings from past DVCon India conferences, visit here.
The first DVCon Taiwan was held in September in Hsinchu. The full-day event was well attended by the local community. There were four keynotes focused on standards, autonomous verification, smart verification, and leveraging AI. A thought-provoking panel discussion offered attendees thoughts on how to develop talent for future design and verification needs. DVCon Taiwan 2024 is scheduled for September 10. Visit the website for the most up-to-date information.
SystemC Evolution Fika
SystemC Fikas are full-day virtual workshops and are free to attend. They are referred to as Fikas to honor the Swedish tradition of sharing a coffee, slowing down a bit, and talking about things the participants care about.
The most recent SystemC Evolution Fika was held September 12. Presentations included an update on SystemC IEEE 1666, tracing in SystemC, and SystemC data types. For more information and to view presentations from the Fikas, visit the SystemC events page.
Since its inception, the Accellera-sponsored IEEE Get Program has resulted in nearly 175,000 downloads. The IEEE Get Program provides no cost access of electronic design and verification standards to engineers and chip designers worldwide. For more information and to view the standards available for download, visit the Available IEEE Standards page on the Accellera website.
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