Community Newsletter: February 2026

IN THIS ISSUE:

Message from the Chair: Welcoming a New Year of Progress and Collaboration
Recent Press Coverage: “What is the Accellera Systems Initiative?”
Join Accellera at DVCon U.S. 2026
- Portable Stimulus Modeling Patterns
- SystemC - What’s New and What’s Next?
- Accellera-sponsored Evening Reception
- Breakthrough in CDC/RDC Verification
- IP-XACT Demystified
Upcoming Events
- DVCon U.S. 2026
- Submit your Proposals for the Next SystemC Fika Virtual Event
- First Hands-On SystemC Sprint Coming in April!
Stanley J. Krolikoski Scholarship Open for Applications
More Resources
- DVCon Archives from Around the Globe
- Hundreds of Videos Available On-Demand on Accellera’s YouTube Channel
- Standards Available Through IEEE GET Program

Message from the Chair

Welcoming a New Year of Progress and Collaboration

I hope everyone had a restful and joyful holiday season. As we begin 2026, I’d like to extend a warm welcome back and share a few important updates from across our Accellera community.

Please join me in welcoming our newest members, ChipAgents and Parade Technologies. We’re excited to have them on board and look forward to their contributions to our collaborative standards development efforts.

We also welcome Deepak Manoharan of Arm to the Accellera Board of Directors. Deepak brings valuable insight and leadership, and we’re pleased to have him join us in shaping Accellera’s future.

At our annual board meeting, all officers were re-elected. I’m honored to continue serving as Chair of Accellera. I’m also pleased to announce the continuation of our strong leadership team:

Dennis Brophy remains our Vice Chair and continues to chair the Promotions Committee
Martin Barnasconi continues as Corporate Secretary and Technical Committee Chair
Aparna Dey remains our Treasurer
Lynn Garibaldi, Executive Director, has been appointed Chair of the IP Rights Committee

Together, this team remains committed to advancing our mission and supporting the incredible work of our community.

Looking ahead, we’re excited to share that the Clock Domain Crossing (CDC) Working Group is nearing completion of its first Language Reference Manual. We expect the new CDC standard to be available shortly, providing much-needed clarity and interoperability for CDC/RDC design and verification flows.

As always, we welcome your ideas for new standardization efforts, especially as emerging challenges in AI, safety, and supply chain complexity drive the need for collaborative solutions.

Finally, we look forward to seeing many of you at DVCon U.S., taking place next month in Santa Clara. We’ll be hosting a reception on Monday evening, and I hope you’ll join us to connect with colleagues and celebrate the exciting work happening across our ecosystem.

Thank you for your continued support, and best wishes for a successful and inspiring 2026!

Sincerely,
Lu Dai, Accellera Systems Initiative Chair

Recent Press Coverage

Accellera’s Chair Lu Dai chats with Bill Wong of Electronic Design to explore Accellera’s pivotal role in the EDA ecosystem. In this interview, Lu describes how Accellera operates as a global, member-driven organization advancing design and verification productivity through open, vendor-neutral standards. By uniting engineers, EDA vendors, IP providers, and end users, Accellera develops and advances standards such as SystemVerilog, UVM, SystemC, UPF, and Portable Test and Stimulus, that often transition to the IEEE for long-term governance, while initiatives like the IEEE GET Program help to expand global access.

Lu also highlights how Accellera stays aligned with fast-moving trends including AI, low power, and safety-critical systems through active working groups, and how its global DVCon conferences foster technical exchange and community collaboration, all supported by a forward-looking roadmap that continues to evolve standards, launch new initiatives, and invest in education and outreach.

Read the full interview: “What is the Accellera Systems Initiative?”
Electronic Design, January 22, 2026

Experience the Future of Design & Verification with Accellera at DVCon U.S. 2026

We invite you to join Accellera throughout the conference and exhibition as we host three workshops, one tutorial, and a special evening reception at DVCon U.S. 2026.

March 2–5, 2026
Hyatt Regency Santa Clara

Portable Stimulus Modeling Patterns (Practical Tips for Adopting PSS)

Monday, March 2 9:00-10:30 a.m., Grand Ballroom D

The Portable Stimulus Standard (PSS) offers a scalable solution to the demands of SoC-level verification by enabling engineers to model verification intent at a higher level of abstraction and apply constrained-random techniques at the scenario level. This allows for automated generation of diverse test cases across multiple execution platforms, dramatically improving reuse and coverage.

This workshop will equip attendees with a deeper understanding of PSS fundamentals and demonstrate how to apply it to real-world verification challenges. Through practical examples, participants will learn how PSS can revitalize legacy flows, streamline test creation, and unlock new capabilities for system-level verification.

Whether you're looking to extend your current methodology or future-proof your verification strategy, this session will show how PSS can help you meet today’s challenges—and tomorrow’s—with confidence.

SystemC - What’s New and What’s Next?

Monday, March 2 11:00 a.m.-12:30 p.m., Grand Ballroom D

SystemC has long served as a foundational technology for full-system simulation and virtual platform development. While the standard has matured over many years, the continued evolution of modern system architectures and tooling has made it clear that SystemC must keep advancing to remain effective and interoperable across diverse use cases. This presentation will cover:

The current state of the SystemC standard, with a focus on the updates introduced in IEEE 1666‑2023
An introduction to SystemC CCI, including the goals of the working group and the upcoming standardized APIs for inspection and control
Lessons learned from widely used open‑source full‑system simulation frameworks such as QEMU
An outlook on the future direction of SystemC and CCI, the challenges facing the industry, and the steps required to overcome them

The session will conclude by leading into a Birds‑of‑a‑Feather (BoF) discussion, inviting participants to help shape the next steps for SystemC and its ecosystem to ensure the community is prepared for the future.

Join Accellera for an Evening Reception!

Monday, March 2 5:00-6:00 p.m. Grand Ballroom/Exhibit Hall

Join us to celebrate exciting developments at Accellera and enjoy raffle prize drawings for attendees.

Breakthrough in CDC-RDC Verification Defining a Standard for Interoperable Abstract Model

Thursday, March 5 9:00 a.m.-12:30 p.m., Grand Ballroom D

The Accellera Clock Domain Crossing (CDC) Working Group is developing a standard CDC-RDC IP-XACT/TCL model that enables portability and reuse across verification tools.

This tutorial will review CDC-RDC fundamental concepts and constraints, outline the reference verification flow, and describe the goals, scope, structure, and deliverables of the Accellera CDC Working Group. Attendees will gain insight into the development of the standard abstract model and its intended usage.

An update on the current status of the latest Language Reference Manual (LRM) will also be presented.

IP-XACT Demystified: An In-Depth Training on the IEEE 1685-2022 IP-XACT Standard

Thursday, March 5 1:30-3:00 p.m., Grand Ballroom D

As System-on-Chip (SoC) designs grow in scale and complexity, integration teams face significant challenges in managing registers, memory maps, IP packaging, and verification collateral. Traditional methods based on spreadsheets or proprietary formats often result in inconsistencies, delays, and costly rework.

IEEE 1685-2022 (IP-XACT), developed by Accellera, provides a vendor-neutral framework to describe, package, and integrate IP. The 2022 revision introduces an updated schema, richer register and memory map support, and enhanced mechanisms for capturing hierarchy and connectivity. These improvements enable consistent design data exchange across design, verification, and software teams, while supporting greater automation and reuse.

This training workshop provides participants with a practical understanding of IP- XACT 2022 and how to apply it in real SoC projects.

Scholarship Applications Open

Applications are now open for the Stanley J. Krolikoski Scholarship and will be accepted through April 30, 2026. This scholarship supports undergraduate students pursuing degrees in electrical engineering or computer science at accredited colleges and universities. For full details, eligibility requirements, and access to the application, please visit the Accellera scholarship page.

Upcoming Events

DVCon U.S. 2026

Welcome Message from DVCon U.S. 2026 General Chair, Xiaolin Chen

It is my great honor and pleasure to serve as the DVCon U.S. Conference General Chair. On behalf of the steering committee, a warm welcome to DVCon U.S. 2026! This year will be the first time we are at the new venue, the Hyatt Regency, Santa Clara, California, located in the heart of Silicon Valley. I am incredibly pleased to say that this has allowed us to expand the capacity for all the technical session rooms, as well as provide attendees with a much larger exhibition hall.

We are immensely proud to continue our tradition of providing an annual technical forum that serves the practicing design verification community. Now in its 38^th year, DVCon U.S. has long established itself as the must-attend premier Design and Verification Conference and Exhibition.

We have an exciting program in store for attendees this year with a fully packed schedule over four days. It should not come as a surprise to anyone that many of the topics will be centered around AI!

We have two extremely exciting Industry Keynotes on the schedule. The first keynote on Tuesday afternoon “Verification, Validation and HW/SW Challenges with Complex Chiplet-based Systems” will feature Abhi Kolpekwar, Senior Vice President Digital Verification Technology from Siemens EDA, Jean-Marie Brunet, Senior Vice President Hardware Assisted Verification from Siemens EDA, and a special guest speaker Alon Shtepel, Senior Director ASIC Verification and Emulation from Micron Technology. The second keynote is the Invited Industry Keynote on Wednesday afternoon “From Pixels to Tokens: Chip Design and Verification in the Era of AI” that will be presented by Stuart Oberman, Vice President from Nvidia. Both keynote presentations will offer insights into the vision and direction of design and verification for the future, especially with the disruption to workflows at all levels by AI.

Our panel chair, Ambar Sarkar, has organized a thought-provoking panel session, “Is AI the Key to Ending the Verification Bottleneck?” This will be an opportunity for attendees to participate and interact with panelists by asking questions during a live discussion.

Monday and Thursday will continue to be designated to tutorials and workshops, and I am pleased to share that this year’s program features more tutorials and workshops than in previous years. Shekar Chetput, the Tutorial and Workshop Chair has arranged an excellent program for us. The Accellera tutorials and workshops offer the latest in standards development in Clock Domain Crossing, Portable Stimulus, IP-XACT, and SystemVerilog Mixed-signal interfaces and applications. In addition, many of the other tutorials and workshops are on the topic of agentic AI across RTL design, verification, and debug. I hope you take advantage of these opportunities to take a deeper look at what the industry has to offer and how these products and technologies can be used in methodologies shaping the next generation of electronic system design.

We appreciate all of the submissions to the conference, as we had a record number of submissions this year. Please keep contributing so the whole community can benefit from everyone sharing and learning. Dave Rich, the Technical Program Chair, along with a group of volunteer technical program committee members, have extensively reviewed and selected the best submissions, putting together outstanding technical sessions for attendees. Since AI is pervasive in all design and verification flows, we have made some changes to the technical session format this year. Instead of having a separate AI track, we have interwoven AI-related talks into the respective technologies that can be applied in design and verification projects.

To continue with our new tradition at DVCon U.S., there will be a Poster Ninja Warrior session on Wednesday, which will include the highest rated four posters (voted on by attendees) battling it out for top honors. Each Poster Warrior will be given five minutes to present their poster, followed by an insightful Q&A from a panel of expert judges. Audience participation and reaction are highly encouraged as it is an integral part of the judging process, creating a dynamic and interactive event.

We look forward to your votes for the best paper and best poster awards at the reception after the last program session on Wednesday.

We hope all the attendees will fully enjoy the keynotes, outstanding technical sessions, networking experience, and the opportunity to preview the latest industry design and verification tools in a variety of exhibitions.

To put together a conference of this magnitude requires tremendous effort. I would like to express my sincere gratitude to the Steering Committee and the Technical Program Committee, with the support of Conference Catalysts, for their tireless efforts to put together an excellent program for attendees. I would also like to thank all of the sponsoring organizations for their generous financial support. Lastly, I want to thank all conference participants for their contributions in helping to build the foundation of this conference.

I look forward to seeing you at DVCon U.S. 2026!

Xiaolin Chen
DVCon U.S. 2026 General Chair

For a complete program schedule, including exhibition hours, visit the DVCon U.S. 2026 website.

Registration is open. Registration for the keynotes, panel, and exhibits is free.

Experience SystemC in Action! Join the Hands-on SystemC Sprint

The Accellera SystemC Sprint is a practical, code‑focused event where participants actively develop and advance SystemC. Unlike a conference or workshop, this in-person event is designed for collaborative implementation, discussion, and rapid prototyping. Participants are expected to write, review, and discuss real SystemC code together with fellow contributors and experts.

The main topic at this sprint is to develop a proof-of-concept for the SystemC CCI Control Interface. In addition, the SystemC experts will kick-off the Accellera Summer of Code 2026 program.

The Accellera SystemC Sprint takes place on April 22 at the RWTH Aachen University in Germany. More information and registration can be found at systemc.org.

SystemC Evolution Fika – Call for Presentations is now open

Are you working on innovative methodologies, tools, or applications using SystemC? Do you have insights, best practices, or research you’d like to share with the community? Join us at the next SystemC Evolution Fika on April 23, 2026, the online knowledge-sharing event for SystemC enthusiasts!

We’re looking for presentations (20–30 minutes) on topics such as:

Hardware/Software co‑design and co-verification
Creating Virtual Prototypes and/or Digital Twins
Application of SystemC in industrial or research projects
Using SystemC beyond SoC (e.g., systems-of-systems modeling)
Heterogeneous modeling and simulation using SystemC and its extensions (e.g., AMS, TLM, CCI, etc.)

Send a brief abstract (2–3 paragraphs) before April 2, 2026, to systemc-evolution-day@lists.accellera.org. Abstracts will be reviewed by the SystemC Fika organization committee. Submitters will be notified by April 6, 2026, whether their presentation is accepted. More information and registration can be found at systemc.org.

More Resources

Explore Hundreds of Accellera and DVCon Videos On-Demand

Find the latest videos from our working groups, industry events and technical presentations on Accellera’s YouTube channel. We also host an extensive collection of videos on our Vimeo channel. Check out both platforms and explore content that interests you.

For more videos from our DVCon conferences, visit the DVCon Papers, Posters, Presentations and Video Archive site.

IEEE GET Program – Download Standards at No Cost

The IEEE GET Program provides engineers and chip designers worldwide with no cost access to electronic design and verification standards. For more information and to view the standards available for download, visit the Available IEC/IEEE Standards page on the Accellera website.