Community Newsletter: October 2020
IN THIS ISSUE:
- Message from the Chair
- A year unlike any other; working groups making great progress
- Working Group Updates
- IPSA MITRE Contribution
- Portable Stimulus Update on v2.0
- Event Updates
- DVCon Europe 2020
- SystemC Evolution Day 2020
- Accellera Day India 2020
- DVCon U.S. 2021
- DVCon China 2021
- DVCon U.S. 2020 Accellera Day Videos Available
- Functional Safety Working Group Video from Virtual DAC Now Available
- IEEE Get Program Update – Almost 115,000 Downloads!
With the entire globe facing a crisis most of us have not seen in our lifetimes, I’d like to extend my gratitude and appreciation to our community for coming together and continuing to persevere through the difficult challenges brought about by the COVID-19 pandemic.
With most of our teams already collaborating remotely, Accellera has been extremely fortunate that the crisis has had minimal impact on the progress in our working groups.
Our Portable Stimulus Working Group (PSWG) has continued to meet via teleconference on a weekly basis and is preparing for the public review of its 2.0 standard toward the end of the year. Our UVM-AMS and Functional Safety Working Groups are both making tremendous headway on their Design Objective Documents, and IP-XACT is gearing up for a 2.1 update that will be available next year.
With the health of our community of paramount importance, our events in the next few months will be virtual. DVCon Europe and SystemC Evolution Day will be held at the end of this month on an exciting, interactive platform showcasing the latest Accellera standards and how they are being adopted and applied in the industry.
DVCon India will not be held in person this year, but the team is excited to bring Accellera Day India online December 2 & 3. DVCon U.S. will be held virtually in March and plans for the four-day conference are well underway.
DVCon China is planning an in-person event for its local design and verification community in April 2021. We are hopeful that this will be the beginning of returning to some type of normalcy and a nearing of the end of an exceedingly difficult time for everyone.
We are looking forward to in-person events coming back around the world, but for now we must all be vigilant and take care to avoid the risks associated with COVID-19.
From all of us at Accellera, we wish you safety and good health.
Lu Dai, Accellera Systems Initiative Chair
IP Security Assurance: IPSA MITRE Contribution
The Accellera IP Security Assurance (IPSA) Working Group, under chair Brent Sherman, has just announced a partnership with MITRE in support of the MITRE Hardware Common Weakness Enumeration (HW CWE) that was launched earlier this year. The proposed IPSA standard requires a Security Weakness Knowledge Base repository to hold the security concerns associated with hardware IP. IPSA’s collaboration with the MITRE HW CWE is a great example of such a database. The IPSA Known Security Concerns subgroup, with Mike Borza as chair, has already submitted its first submission on behalf of Accellera and is busy reviewing additional content submissions from the team. Congratulations to the IPSA Working Group on this key component for the Secure IP industry.
Portable Stimulus: Latest News on Portable Test and Stimulus v2.0
The members of the Portable Stimulus Working Group (PSWG) are happy to report that they are making substantial progress on version 2.0 of the Portable Test and Stimulus Standard (PSS). Originally referred to (at DVCon U.S. 2020 and elsewhere) as PSS 1.1, the Working Group decided that the number of new features being added since PSS 1.0a necessitated referring to this new version as a “major release,” hence the 2.0 designation.
With over 100 pages of new material, PSS 2.0 promises to enhance usability based on user feedback from the previous version. The new enhancements can be categorized as follows:
- General Programming Enhancements
- Template types
- Collection types, including lists, maps, associative arrays and more
- Abstract Modeling Enhancements
- Additional activity-level statements, including replicate
- New constraint constructs, including forall and default constraints
- Procedural Constructs
- Control-flow constructs for exec blocks and native PSS functions
- Greatly enhanced portability of realization layer code
- New Core Library
- Support for modeling of memory allocation and management
- Support for register modeling
The PSWG is planning to release a Public Review version of PSS 2.0 in mid-November to gather feedback from the user community on these powerful enhancements, in advance of the official release of the standard, due in early 2021. We encourage everyone to download the Public Review version when it is available and let us know what you think about it. In the meantime, we will continue working to ensure that PSS 2.0 provides the next level of verification productivity to verification engineers across our industry.
For the latest overview tutorial on the standard, please click here.
DVCon Europe 2020
The 7th annual DVCon Europe will be held virtually October 27 & 28. The in-depth two-day program is now available online and offers attendees four keynotes, 24 paper presentations, 11 poster presentations, 13 tutorials, and two panel sessions.
“We are proud that the DVCon Europe 2020 program hosts four luminary industry speakers from ARM, Intel, Veriest, and Volkswagen providing their perspectives on the digital transformation our industry is facing,” stated Joachim Geishauser, DVCon Europe 2020 General Chair.
“This digital transformation continues to gain momentum and is changing our daily lives, changing the way we work, collaborate, communicate, and commute. As a common theme across the keynotes, you will hear about how to develop and verify exciting new products, combining innovative hardware and software architectures. This requires unprecedented parallel hardware and software development, with a close interaction between the teams.
“The keynote speakers will be sharing their insights into the adoption of new methodologies and verification approaches and will discuss how the formerly separated disciplines of hardware and software are adapting to a new "system thinking." Beside the keynotes, the 7th edition of DVCon Europe again offers a fully packed two-day technical program including tutorials, panels, posters, papers, and an attractive virtual 3D world to enable networking and interaction,” Geishauser concluded. Read the complete Welcome Message from the General Chair.
More information on the keynote topics and speakers can be found here.
To view the papers and presentations from DVCon Europe 2019, visit here.
SystemC Evolution Day 2020
The fifth annual SystemC Evolution Day will be held virtually on October 29 following the virtual DVCon Europe conference. The online gathering of the SystemC community will include technical presentations and creative discussions and debates to advance the SystemC ecosystem.
In several in-depth sessions, selected current and future standardization topics around SystemC will be discussed to accelerate their progress for inclusion in Accellera/IEEE standards.
SystemC Evolution Day is intended as a lean, user-centric, hands-on forum bringing together experts from the SystemC user community and the Accellera working groups to advance SystemC standards.
For more information about SystemC Evolution Day, including past presentations and summaries, and to view the program for 2020, visit here. The full-day workshop is free to attend, but registration is required.
Accellera Day India 2020
By Sanjay Muchini, Accellera Day India 2020 General Chair
I take great pleasure in inviting you to Accellera Day India – Virtual Edition, scheduled on December 2nd and 3rd, 2020!
The Accellera Day India 2020 technical program provides multiple opportunities to interact with industry and academia domain experts delivering keynote speeches and tutorials. It is truly a privilege to present the Accellera Day 2020 India event, virtual this time, that will provide an excellent platform to survey and learn the latest in design and verification technologies, methodologies, and tools from the best in the industry.
This year we have tailored Accellera Day India as an in-depth two half-day virtual technical program on December 2nd & 3rd. The conference has keynotes from industry & academia, Accellera working group updates, and tutorials. The technical conference targets latest trends and challenges on Automotive domain, Functional Safety & Security, RISC-V architecture verification, UVM standards, Portable Stimulus standard, and Formal Verification. Tutorials will focus on deep technical concepts, challenges, and solutions relevant to most of the engineers working in the verification domain. The examples will help engineers related to and solve some of the challenges they are facing in their day-to-day activities.
The event is a must attend for industry leaders, engineering managers, system architects, verification experts, SoC integrators, chip designers, EDA vendors, CAD and IP developers, emulation and post-Si validation engineers, VIP developers, and firmware engineers working on the latest cutting edge semiconductor products.
For 2020, our focus remains unchanged: to offer a compelling event where technical experts active in system-level design and verification can interact, share best practices, and learn the latest design and verification methodologies, language, and standards to create competitive advantage to their organizations.
The India steering committee wishes you a warm welcome and an enjoyable Accellera Day India 2020!
To register and find more information on the program, speakers, and sponsorship opportunities, please visit the Accellera Day India page.
For more insight into the benefits of Accellera Day India, read the blog by Dennis Brophy, Accellera’s Promotions Committee Chair.
DVCon U.S. 2021
“Our 33rd annual DVCon will continue the tradition of the industry’s must-attend design and verification event,” stated Aparna Dey, DVCon U.S. 2021 General Chair. “We’ll have opportunities for practicing engineers and managers to learn and engage with presenters online, as well as gain valuable, practical knowledge, methods, and emerging trends that can be applied to their current and future projects.”
For more information on the virtual conference, visit here.
To view the complete papers and presentations from DVCon U.S. 2020, including some with audio recordings, visit the follow up virtual conference website.
DVCon China 2021
DVCon China will be held Spring 2021 with in-person attendance for the local design and verification community. Stay tuned for more details in the coming weeks.
- Tutorial: “Portable Stimulus: What’s Coming in 1.1 and What it Means for You”
- Luncheon panel: “The Portable Stimulus Standard”
- Short Workshop: “An Introduction to the Emerging IP Security Assurance Standard”
- Short Workshop: “How HLS and SystemC is Delivering on its Promise of Design and Verification Productivity”
Accellera’s Functional Safety Working Group Addresses Standardization Efforts to Improve Automation, Interoperability, and Traceability
Accellera’s Functional Safety Working Group (FSWG) presented an overview at the virtual 57th Design Automation Conference on the scope, needs, and goals defined by the FSWG, including developments since its formation.
Introductions by Accellera Chair Lu Dai, Technical Committee Chair Martin Barnasconi, and FSWG Chair Alessandra Nardi were followed by informative presentations by functional safety experts focusing on specific perspectives, challenges, and opportunities.
Since its inception, the Accellera-sponsored IEEE Get Program has resulted in close to 115,000 downloads. The IEEE Get Program provides no cost access of electronic design and verification standards to engineers and chip designers worldwide. For more information and to view the standards available for download, including the newly released IEEE 1800.2-2020, visit the Available IEEE Standards page on the Accellera website.
2020 Global Sponsors
Are you interested in becoming a Global Sponsor? Find out more about our Sponsorship Package.
Copyright 2020 Accellera Systems Initiative