[sv-bc] My issues to analyze

Hi, all,

I've done my issues analysis:

943 	Major	Syntax of assignment patterns needs clarification
948	Major	Static type methods
950	Major	Incorrect statement about array slices
951	Major	tagged_union_expression (BNF)
953	Major*	Defparam of struct parameter member
956	Minor	25.2 (defparam) inaccurate and has multiple typos
957	Major	"default initial value" unclearness
959	Major	&&& operator  and missing ||| operator
965	Minor	Name from example should use constant-width typeface
(6.3.2.1) 
			Proposal exists for 965 in form of change the
font.
967	Minor	Typo in 6.3.3?


1114	Minor	1.2: clarify terms like "undefined"
1115	Minor	3.7 and 7.10, 7.13: need xrefs
1116	Minor	D.3-D.6: delay modes not defined
1117	Minor	15: notifier is reg only?
1118	Minor	15.5.1-15.5.4: neg timing checks only?
1119	Minor	19.3: Preprocessor macros with strings
1125	Minor	Add 'pragma compiler directive
1126	Minor	Add language defined attribute capability
1127	Close	Add shared declaration mechanism to Verilog - packages
1128	Minor	Non-blocking event trigger
1130	Minor	non_zero_unsigned_number and non_zero_decimial_digit is
not supported by industry standard tools
1132	Minor	allow force on memory word or bit-/part-select of vector
variable
1133	Minor 	allow reverse part-select [lsb:msb]
1134	Minor	Add localparam to ANSI-type param list
1135	Minor	module instance without parentheses