Interface Working Group


To identify and standardize multi-abstraction and multi-domain interfaces that enable complete, high performance verification environments to be constructed.

This working group is currently inactive. For more information, please contact us.


The goal of the Interface Working Group is to reduce the effort necessary to get a system into an emulation or prototyping environment for verification. In order to do that, the models at the boundaries - transactors - have to be as similar as possible to those that would have been used in a simulation environment and must be portable among emulation vendors. Efficiency across the interface is paramount to getting the best possible utilization of the hardware, so capabilities add control over when and how traffic moves around the system.

The latest version of the standard, SCE-MI 2.4, was approved in March 2017. SCE-MI 2.4 is a minor release that tightened up some language and formatting in the document. The SCE-MI function-based interface allows a subset of the SystemVerilog DPI to be used. In the past, the standard has fully supported functions, but in this release, it is extended to include zero time consuming tasks. Also in this release a new capability allows the HVL-side application to stop a simulation. This is done by adding the appropriate VPI calls to the supported list.

The direct memory interface (DMI) has been extended to add several functions. These include the addition of a byte-aligned interface, a file I/O capability and the addition of functions for loading patterns into, or clearing, the memory. The semantics associated with the prefetch of the word interface for the DMI was clarified and some minor bugs were fixed.


SCE-MI 2.3 expanded the set of SCE-MI compliant DPI function argument data types, extends the debug interface to provide C-side access to HDL-side registers and adds a new mechanism that enables a SystemVerilog HVL-side testbench to call DPI functions to HDL-side SystemVerilog or vice versa.

SCE-MI 2.2 was approved in October 2013 and added a clocked and unclocked pipe interface to make data streaming easier. It also added its first debug interface, a direct memory interface.

Version 2.1 was approved by the Accellera board in January 2011 and enables a model developed for simulation to run in an emulation environment and vice versa. Version 2.1 has added support for a subset of the SystemVerilog Direct Programming Interface (DPI) and built a streaming, variable length messaging system on top of this, which reduces the number of synchronizations when compared to other available methodologies.

In May 2007, the Accellera Board approved the 2.0 version of the specification. This version added two new use models including a subset of the SystemVerilog DPI capabilities and a new high-performance pipes interface.

In January 2005, the working group approved the 1.1 version of this specification; it was ratified by the Accellera board in April 2005.

The first part of the SCE-API (Standard Co Emulation API) standard, namely the modeling interface (or SCE-MI for short), was first approved by Accellera on May 29th 2003. This was the 1.0 version of the specification.

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This working group is currently inactive. For more information, please contact us.