Universal Verification Methodology (UVM) Working Group
(Formerly Verification Intellectual Property (VIP) Working Group)
To define standard technology and/or methods to realize a modular, scalable and reusable generic verification environment.
The goal of the Universal Verification Methodology (UVM) Working Group is to improve design productivity by making it easier to verify the design components with a standardized representation that can be used with various verification tools.
The UVM Working Group is responsible for the definition and development of the Universal Verification Methodology (UVM) standard.
Chair: Justin Refice, NVIDIA
Vice-Chair: Mark Strickland, Cisco
Secretary: Jamsheed Agahi, Semifore
Verification components and environments are currently created in different forms, making interoperability among verification tools or geographically dispersed design teams time consuming and error prone. The results of the UVM standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting IP for each new project or electronic design automation tool, as well as make it easier to reuse verification components. Overall, the UVM standardization effort will lower verification costs and improve design quality throughout the industry.
In July 2015, UVM 1.2 was submitted as a contribution to the IEEE P1800.2™ working group for further standardization and maintenance. The P1800.2 working group commenced work at its first meeting on August 6, 2015. The Accellera UVM Working Group delivered the UVM Library (SV) Reference Implementation matching the 1800.2 LRM in June 2018. The library can be downloaded here.
The IEEE 1800.2-2017 standard is available free of charge from the IEEE Get program, courtesy of Accellera. Download it here.
The IEEE 1800 SystemVerilog Hardware Design and Verification Language (HDVL) is a language of choice for modern design and validation. Yet, there isn’t a standard to create and use VIP written in the SystemVerilog language. The UVM WG will offer the next generation of benefits from SystemVerilog to verification engineers.
Verification solutions are ubiquitous, differing from company to company and among separate organizations within companies. Commercial tool suppliers do not support all the verification solutions in use today. The result is that there are many different methods for doing the same thing, requiring retraining and conversion costs. Interoperable VIP components reduce the cost of using and re-using VIP and improve the quality of design verification by eliminating translation errors.
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