Community Newsletter: August 2024

IN THIS ISSUE:

• Message from the Chair
• Accellera Working Groups are Fired Up!
• News from Accellera Working Groups
• Portable Stimulus 3.0 Available!
• New Federated Simulation Working Group Formed
• Clock Domain Crossing 0.3 Public Review Open
• UVM for Mixed Signal Standard Available for Public Review
• UVM-SystemC 1.0-beta6 Available for Public Review
• Recent Press Coverage
• Accellera Announces Federated Simulation Standard Working Group, Electronics Weekly
• System-Level Simulations, Sub-System Digital Twins, 2.5D Heterogeneous Integration, UCIe and CMOS 2.0, Semiconductor Digest
• Upcoming Events
• DVCon Taiwan September 10
• DVCon India September 18-19
• DVCon Europe October 15-16
• SystemC Evolution Day October 17
• DVCon U.S. 2025 – call for contributions is open!
• New Videos Available
• Portable Stimulus Tutorial
• DVCon U.S. 2024 Proceedings
• Recent Event Wrap Up
• DVCon Japan
• DAC Luncheon Focused on Portable Stimulus
• SystemC Fika
• IEEE Get Program Update

 

Message from the Chair

As the world experiences an exceptionally hot summer, Accellera’s working groups are equally fired up in their pursuit of hitting our release targets. I’m thrilled to share some of the key milestones and ongoing efforts that are helping to shape the future of design and verification productivity in our industry.

Portable Test and Stimulus 3.0 has officially been released following an extended public review. This is a significant step forward, and I want to thank everyone involved for their dedication and hard work.

We also have two important public reviews currently in progress: CDC (Clock Domian Crossing) and UVM-MS (Universal Verification Methodology for Mixed-Signal). Your feedback is crucial, so please visit our community forums to provide your input and comments.

The UVM for SystemC group has just released its beta6 version, an exciting development for the SystemC community.

The Federated Simulation Working Group is the newest member of the Accellera family. Despite being in the initial stages, the work is progressing rapidly, and we anticipate that Federated Simulation will be a major focus at the upcoming DVCon Europe in October. This new initiative is already attracting significant attention from both our traditional members and players in the broader industry. We are delighted to announce that Ford Motor Company has joined our Board of Directors and is participating in the new working group. We’re also seeing strong interest from other members of the initial proposed working group who are approaching Accellera for membership.

In addition to all our standards work, Accellera sponsors six DVCon conferences around the world that have developed into an international phenomenon. DVCon Japan hosted its second in-person event last week; its followed closely by the second edition of DVCon Taiwan, which will be co-located with RISC-V Taipei Day. Meanwhile, DVCon India continues to grow, entering its 11th year, including the first two years as Accellera Day India.

As you know, our standards are only as good as the input we receive from the community. Whether you have suggestions for improvements to existing standards or if you have ideas for new ones, I encourage you to reach out to us through the many official Accellera online channels, working group members, or at a DVCon near you. Our wonderful volunteers are always eager to hear from the community.

I look forward to seeing you at one of the upcoming DVCon conferences near you.

Sincerely,
Lu Dai, Accellera Systems Initiative Chair

 

News from Accellera Working Groups

Portable Test and Stimulus Standard 3.0 Now Available!

Ushering in a new era of verification efficiency, Accellera’s Board of Directors has approved the Portable Test and Stimulus Standard 3.0 for immediate release.

“The latest enhancements to the Portable Test and Stimulus Standard are set to significantly boost design productivity for system-level design and verification engineers worldwide,” stated Lu Dai, Accellera Chair. “I want to extend my congratulations to the PSS Working Group for their exceptional dedication and effort in delivering this updated version to engineers around the globe.”

PSS defines a means to create a single representation of stimulus and test scenarios, usable by a variety of users across many levels of integration under different configurations. This representation facilitates the generation of diverse implementations of scenarios that run on a variety of execution platforms, including simulation, emulation, FPGA prototyping, and post-silicon testing. By defining scenarios in a single representation, users can specify intent once and observe consistent behavior across multiple implementations.

This standard offers a declarative environment designed for abstract behavioral descriptions using actions, inputs, outputs, and resource dependencies, and integration into use cases including data and control flows. These use cases capture verification intent that can be analyzed to produce a broad spectrum of valid scenarios for multiple execution platforms. Additionally, the standard includes a preliminary mechanism to capture the programmer’s view of a peripheral device, independent of the underlying platform, which further enhances its portability and versatility.

PSS 3.0 adds many new features, corrects errors, clarifies aspects of the language and semantic definitions, and much more. The most substantial feature added to PSS 3.0 is support for behavioral coverage where several scenarios can be generated from a single PSS specification. These scenarios vary in action order and data. Coverage statements identify a key action order and data combination that must be observed to exercise key functionality. The specification of the observed action order - and possibly the data related to this ordering - is called behavioral coverage.

Other substantial new features include:

• Support for “sub-string operator” and string methods
• Support to allow collection of reference types
• Support to allow platform qualifiers on function prototype declarations
• Clarified static const semantics
• Support for comments in template blocks
• Support for yielding control with cooperative multitasking
• Address space group
• PSS-SystemVerilog mapping for PSS lists
• “Formal semantics of behavioral coverage” annex

Download Portable Test & Stimulus Standard 3.0 >

Members of the working group presented a tutorial, “Efficient Portable Programming-Sequence Development with PSS,” during DVCon U.S. 2024. The tutorial is divided into sections that include what portable stimulus is, the motivation behind the standard, developing reusable test content at the block level, sub-system and SoC-level testing with PSS, and post-silicon testing with PSS.

Accellera has additional resources available to help you learn about portable stimulus and how it can positively impact your design and verification methodology. Additional information is available on the Portable Stimulus Working Group page. Feedback on the standard can also be provided through the Portable Stimulus Community Forum.

Federated Simulation Standard Working Group

The Accellera Board of Directors recently approved the formation of the Federated Simulation Standard (FSS) Working Group (WG). The charter of the new working group is to establish cross-industry collaboration to improve the interoperability of product and environment simulation, models, and components using existing and new open standards.

“The intent of the Federated Simulation Standard is to develop a standard and open infrastructure to enable interoperability of established modeling and simulation standards, technologies, and tools as part of a distributed, orchestrated, simulation ecosystem,” stated Martin Barnasconi, Accellera Technical Committee Chair and Chair of the FSS Working Group. “A standardized interface will enable interoperability of modeling and simulation throughout the product lifecycle.”

As part of the development of the standard and open infrastructure, the FSS WG targets alignment with other standards such as ED-247 used in avionics, FMI/FMU applied in automotive, and SMP2 used in the space industry. To take advantage of cross-industry synergies, the WG also aims to align with open collaboration and innovation consortia.

Accellera has also established the Federated Simulation User Group for those that are not currently Accellera members but are interested in learning more about various projects within the community, collaboration with other industries and organizations, and the standardization effort planned in the Accellera FSS WG.

Visit the Federated Simulation Standard Working Group page for more information.
For information regarding the Federated Simulation User Group, including upcoming meetings, view this presentation.

Clock Domain Crossing Working Group

The Clock Domain Crossing (CDC) Working Group has released draft standard 0.3 for public review. The purpose of this standard is to provide the electronic design automation (EDA), semiconductor, and system design communities with a well-defined specification for unified handling of CDC by vendor tools used across IPs and SoCs.

With this interface standard, every IP developer’s verification tool of choice is run to verify and produce collateral, and a standard format is generated for SoCs that used a different tool.

Highlights of the latest draft include:

• Updates to CDC specifications based on public feedback
• Added support for RDC specifications to complement existing CDC properties
• Added IP-XACT and TCL format information
• Examples of complex cases that will be covered in the next version of the LRM

Download the draft here >

The CDC Working Group encourages the community to participate in the review and provide feedback via the CDC Community Forum. The public review is open through September 9, 2024.

For more background on the standard, view the workshop presented during DVCon U.S. 2024, “Hierarchical CDC and RDC Closure with Standard Abstract Models.”

UVM for Mixed-Signal Draft Standard Available for Review!

The Universal Verification Methodology for Mixed-Signal (UVM-MS) draft standard is available for public review through September 9, 2024. It is a comprehensive and unified analog/mixed-signal verification methodology based on the UVM IEEE Std 1800.2™ that improves analog/mixed-signal (AMS) and digital/mixed-signal (DMS) verification of integrated circuits and systems.

This framework enables the creation of mixed-signal verification components and testbenches by extending digital-centric UVM classes and facilitating interaction between class-based and structural environments. The objective is to standardize methods for driving and monitoring mixed-signal nets within UVM. The reuse of proven verification components will in turn increase the productivity of verification teams and improve overall quality. In addition to the standard for review, a UVM-MS test case in the form of a frequency adapter example is available to explore. It demonstrates the UVM-MS capabilities and shows how to use and migrate UVM testbenches to UVM-MS.

The draft UVM for Mixed Signal standard and corresponding test case can be found on the Accellera Drafts Under Review page.

The working group values input and feedback from the community. Please provide comments through the UVM-MS Community Forum.

UVM-SystemC Draft Available for Review

The SystemC Verification Working Group has released the UVM-SystemC 1.0-beta6 proof-of-concept implementation for public review. This is a bug fix release over 1.0-beta5 to address some functionality issues as well as for compatibility with newer compilers and SystemC 3.0.0.

The public review is open through September 6, 2024. The files can be found on the Accellera Drafts Under Review page.
The working group welcomes your feedback. Please provide comments or questions via the SystemC Verification Community Forum.

 

Recent Press Coverage

• Caroline Hayes, editor for Electronics Weekly, attended the Accellera-sponsored luncheon during the 61st Design Automation Conference earlier this summer and covered the Portable Simulus-focused panel discussion, as well as the new Federated Simulation Standard Working Group in her article, “Accellera Announces Federated Simulation Standard Working Group”
• John Blyler recently wrote an article, “System-Level Simulations, Sub-System Digital Twins, 2.5D Heterogeneous Integration, UCIe and CMOS 2.0” for Semiconductor Digest and discussed some of the trends with Lu Dai, Accellera Chair.

 

Upcoming Events

DVCon Taiwan 2024

The second annual DVCon Taiwan will be held September 10th at Amazing Hall, Hsinchu, Taiwan. This year it will be co-located with RISC-V Taipei Day to be held on September 11.

The first keynote, “May the Dependability Be with You: Reliability and Resilience Challenges in SoC Design,” will be presented by Alessandra Nardi, Accellera Functional Safety Working Group Chair and Synopsys Executive Director. Other Keynote presentations include, “AI Accelerated Innovation in Design and Verification,” presented by Simon Chang, Senior Group Director of Cadence, and “Empowering Design and Verification with AI/ML,” presented by Chilai Huang, Senior Director, R&D, Siemens EDA.

A luncheon panel discussion will focus on “AI for Formal Engineering and Formal Engineering for AI – What catches up fast?” It will be moderated by Chung-Yang (Ric) Huang, Professor of the Dept. of Electrical Engineering and Graduate Institute of Electronic Engineering, National Taiwan University.

For the complete program and registration information for both DVCon Taiwan and RISC-V Taipei Day, visit the DVCon Taiwan website.

View the proceedings from DVCon Taiwan 2023.

DVCon India 2024

DVCon India 2024 is just around the corner, promising to be a premier event in India for design and verification engineers. Scheduled for September 18-19 in Bangalore, this year's conference will bring together industry leaders, experts, and enthusiasts to discuss the latest trends, technologies, and challenges in EDA. With a robust lineup of panel discussions, workshops, and tutorials, attendees will have the opportunity to gain insights into the evolving landscape of system design, verification methodologies, and standards.

DVCon India 2024 is set to feature sessions that will offer deep insights into the future of design and verification. The conference will open with a vision talk, “Empowering Innovation: Harnessing Collective Wisdom across Tools, Processes, and People!” presented by Harry Foster, Siemens EDA. It will be followed by the first keynote of the conference presented by Vikas Gautam, Synopsys and Ashok Kumar Natarajan, Google. Together they will present, “The Increasing Verification Horizon in the Era of Pervasive Intelligence.” Attendees will then be treated to a panel discussion, “Strengthening India's Fab Ecosystem: The Critical Role of the Design Community.” The two-day conference is packed with much for attendees to choose from including more keynote presentations as well as another panel discussion focused on “Building RISC-V Systems: An Indian Perspective.”

For the complete program and to register, visit the DVCon India website.

Proceedings from previous DVCon India conferences are available on demand.

DVCon Europe 2024

DVCon Europe returns for its 11th edition October 15-16 at the Holiday Inn, Munich City Center, in Munich, Germany. Registration is open and advance rates are available through September 13.

Welcome Message from DVCon Europe General Chair Mark Burton:

Dear Colleagues and Friends,

Welcome to DVCon Europe 2024!

I have been at every DVCon Europe since its inception over a decade ago, and now I am absolutely honored to play my part as the General Chair, continuing to foster and grow what has become an institution in our industry. This year, I’m really pleased to announce that we are introducing a new SystemC competition, which I know will be a highlight of the conference. So, I’m thrilled to gather once again in this dynamic forum, where innovation, collaboration, and knowledge sharing drive the advancements in the design and verification community.

Our industry is at the forefront of technological transformation, and DVCon Europe stands as a beacon for professionals dedicated to pushing the boundaries of what is possible in Electronic Design Automation (EDA), verification, and embedded systems. This year, we have curated an exciting program that encompasses a diverse range of technical sessions, insightful keynotes, and interactive panel discussions. DVCon Europe has a history of pivotal keynote speakers and this year will be no exception as we welcome two keynote speakers that we’re extremely lucky to have as they are at the forefront of the AI and Automotive industries.

As always, this year’s conference will feature cutting-edge paper presentations and tutorials from leading experts, offering deep dives into the latest methodologies, tools, and techniques. Whether you are a seasoned veteran or new to the field, you will find sessions tailored to your interests and expertise. One of our core missions is to foster an environment where engineers, researchers, and industry leaders can connect and exchange ideas. The research track was a great success last year, and I’m please to say that it has further expanded this year.

For the first time, we will be hosting the DVCon Europe SystemC Modeling Challenge, designed to showcase the skills of our talented attendees. This competition promises to be thrilling, providing participants with an opportunity to demonstrate their expertise and creativity in SystemC. Additionally, we have extended our reception to offer even more opportunities for networking and collaboration providing the perfect setting to connect with peers, discuss ideas, and forge new professional relationships in a relaxed and engaging atmosphere.

There will be additional opportunities for more spontaneous interactions in our exhibition hall which will showcase the latest products and services from top companies in the industry. And finally, our social events are designed to help you build and strengthen professional relationships while having a little fun.

I would like to extend my heartfelt thanks to our sponsors, exhibitors, and the DVCon Europe organizing committee, as well as the technical program committees and reviewers, who are all volunteers. Your unwavering dedication makes this event possible, and your support this year has been, as ever, invaluable.

As we embark on this exciting journey over the next few days, I encourage you to immerse yourself fully in the experience. Engage with the speakers, participate in discussions, and explore the innovative solutions on display. Together, we can drive the future of design and verification.

Thank you for being a part of DVCon Europe 2024. Let's make this an unforgettable event!

Warmest regards,
Mark Burton
General Chair, DVCon Europe 2024

For more information on DVCon Europe, including the full program, visit the DVCon Europe conference website.

Videos from DVCon Europe 2023 are available on-demand as well as proceedings from past DVCon Europe conferences.

SystemC Evolution Day 2024

Co-located with DVCon Europe, the ninth annual SystemC Evolution Day will be held October 17 at the Holiday Inn, Munich, City Centre. The workshop is a full-day in-person event focused on the evolution of SystemC standards to advance the SystemC ecosystem. It is intended as a lean, user-centric, hands-on forum bringing together experts from the SystemC user community and Accellera working groups to advance SystemC standards. Selected current and future standardization topics around SystemC will be discussed.

The program is still being developed. For the latest information and to register, visit the SystemC Evolution Day 2024 event page.

For a complete list of resources, including information on past SystemC events, visit the SystemC community portal SystemC.org.

DVCon U.S. 2025 Call for Contributions is Open!

The 37th annual DVCon U.S. will be held February 24-27, 2025, at the Doubletree Hotel in San Jose, California. The call for extended abstract proposals is open through September 15, 2024, so submit your proposals today! Visit the DVCon U.S. website for the more information and submission instructions for papers, tutorials, panels and workshops.

For inspiration, the proceedings from DVCon U.S. 2024 are available to view on demand.

 

New Videos Available on Demand!

Visit the Accellera videos page and Accellera Vimeo site for the latest videos from our working groups, including the most recent addition, “Efficient Portable Programming-Sequence Development with PSS,” presented by members of the Portable Stimulus Working Group during DVCon U.S. 2024.

DVCon proceedings from conferences around the globe are also available. Recent additions include DVCon U.S. 2024 and DVCon Europe 2023. Visit the DVCon archive site for access to papers, posters, presentations and videos from past conferences.

 

Recent Event Wrap Up

DVCon Japan 2024

The second in-person DVCon Japan was held last week at TKP Garden City Premium, Shinagawa Tokyo.

The keynote, “Semiconductors Change the World — From the National Security and Geopolitical Perspective,” was presented by Yasuhiko Ohta, Nikkei Shinbun.

Accellera Chair Lu Dai and Technical Committee Chair Martin Barnasconi provided an update on Accellera and standards activities via a prerecorded video. Accellera working groups presented two tutorials: one on Clock Domain Crossing, “Hierarchical CDC and RDC closure with standard abstract models” and another on Portable Stimulus. Overall, there were nine tutorial sessions and 20 papers for attendees to choose from.

More information, including the full list of papers and tutorials that were presented, can be found on the DVCon Japan website.

61st Design Automation Conference Luncheon

At DAC, Accellera sponsored a luncheon and panel discussion focused on the recently released Portable Test and Stimulus (PSS) Standard 3.0 while it was in public review.

The interactive panel, moderated by Tom Fitzpatrick, Accellera Portable Test and Stimulus Working Group Vice Chair, provided insight into new features incorporated into version 3.0 of the standard, most notably Behavioral Coverage. Panelists included Dave Kelf, CEO of Breker; Sergey Khaikin, Product Engineering Architect at Cadence; Santosh Kumar, Senior Engineering Manager at Qualcomm; Hillel Miller, Sr. Architect at Synopsys; and Freddy Nunez, Application Engineer at Agnisys. Attendees had an opportunity to ask questions and learn more about the upcoming standard and its benefits.

For more information on the Portable Test and Stimulus Standard, including a list of resources, visit the PSS Working Group page.

SystemC Fika

The most recent workshop on the Evolution of SystemC Standards was held in May. Known as a SystemC Evolution Fika, it is a series of online workshops to discuss the latest SystemC developments and applications. The workshops are referred to as fikas, to honor the fika tradition of sharing a coffee, slowing down a bit, and talking about things that we care about.

The most recent workshop had updates from the SystemC Language, SystemC CCI, and SystemC Synthesis Working Groups.

To view presentations from the Fika in May, as well as past Fikas and SystemC Evolution Day, visit the SystemC events page.

 

IEEE Get Program Update

Since its inception, the Accellera-sponsored IEEE Get Program has resulted in over 194,000 downloads. The IEEE Get Program provides no cost access of electronic design and verification standards to engineers and chip designers worldwide. For more information and to view the standards available for download, visit the Available IEC/IEEE Standards page on the Accellera website.

 

Accellera Global Sponsors

Contact us if you are interested in becoming a Global Sponsor.

 

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